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BSA ACS Testcase checklist

The below table provides the following details

  1. BSA Level at which test run.
  2. BSA rules covered by a test.
  3. SystemReady band(IR, ES and SR) for which test is required.
  4. Runtime environment(UEFI, BareMetal and Linux) where test executes.
  5. Tests for which exerciser is required.
Test No Test Description Level Rule ID IR ES SR UEFI BareMetal* Linux Exerciser Required?
1 Check Arch symmetry across PE L1 B_PE_01 Yes Yes Yes Yes Yes No No
2 Check for number of PE L1 B_PE_02 Yes Yes Yes Yes Yes No No
3 Check for AdvSIMD and FP support L1 B_PE_03 Yes Yes Yes Yes Yes No No
4 Check PE 4KB Granule Support L1 B_PE_04 Yes Yes Yes Yes Yes No No
6 Check Cryptographic extensions L1 B_PE_06 Yes Yes Yes Yes Yes No No
7 Check Little Endian support L1 B_PE_07 Yes Yes Yes Yes Yes No No
8 Check EL1 and EL0 implementation L1 B_PE_08 Yes Yes Yes Yes Yes No No
9 Check for PMU and PMU counters L1 B_PE_09 Yes Yes Yes Yes Yes No No
10 Check PMU Overflow signal L1 B_PE_10 Yes Yes Yes Yes Yes No No
11 Check num of Breakpoints and type L1 B_PE_11 Yes Yes Yes Yes Yes No No
12 Check Synchronous Watchpoints L1 B_PE_12 Yes Yes Yes Yes Yes No No
13 Check CRC32 instruction support L1 B_PE_13 Yes Yes Yes Yes Yes No No
14 Check PAuth if implementation L1 B_PE_15 Yes Yes No Yes Yes No No
15 Check for FEAT_LSE support FR B_PE_25 Yes Yes Yes Yes Yes No No
16 Check SVE2 for v9 PE L1 B_PE_14 Yes Yes Yes Yes Yes No No
51 Check EL2 implementation L1 B_PE_18 Yes Yes Yes Yes Yes No No
52 Check Stage 2 4KB Granule Support L1 B_PE_19 Yes Yes Yes Yes Yes No No
53 Check Stage2 and Stage1 Granule match L1 B_PE_20 Yes Yes Yes Yes Yes No No
54 Check for PMU counters L1 B_PE_21 Yes Yes Yes Yes Yes No No
55 Check VMID breakpoint number L1 B_PE_22 Yes Yes Yes Yes Yes No No
76 Check EL3 implementation L1 B_PE_23, B_PE_24 Yes Yes Yes Yes Yes No No
101 Memory Access to Un-Populated addr L1 B_MEM_02 No No No Yes# Yes No No
102 Mem Access Response in finite time L1 B_MEM_01 Yes Yes Yes Yes Yes No No
103 PE must access all NS addr space L1 B_MEM_05 Yes Yes Yes Yes Yes No No
104 Addressability L1 B_MEM_03, B_MEM_04, B_MEM_06 Yes Yes Yes Yes# Yes Yes No
201 Check GIC version L1 B_GIC_01 Yes Yes No Yes Yes No No
202 Check GICv2 Valid Configuration L1 B_GIC_02 Yes Yes No Yes Yes No No
203 If PCIe, GICv3 then ITS, LPI L1 B_GIC_03 Yes Yes Yes Yes Yes No No
204 Check GICv3 Security States L1 B_GIC_04 Yes Yes Yes Yes Yes No No
205 Non-secure SGIs are implemented L1 B_GIC_05 Yes Yes Yes Yes Yes No No
206 Check EL1-Phy timer PPI assignment L1 B_PPI_00 Yes Yes Yes Yes Yes No No
207 Check EL1-Virt timer PPI assignment L1 B_PPI_00 Yes Yes Yes Yes Yes No No
226 Check NS EL2-Virt timer PPI Assignment L1 B_PPI_00 Yes Yes Yes Yes Yes No No
227 Check NS EL2-Phy timer PPI Assignment L1 B_PPI_00 Yes Yes Yes Yes Yes No No
228 Check GIC Maintenance PPI Assignment L1 B_PPI_00 Yes Yes Yes Yes Yes No No
251 Check MSI SPI are Edge Triggered L1 Appendix I.6 No Yes Yes Yes Yes No No
252 Check GICv2m MSI Frame Register L1 Appendix I.9 No Yes Yes Yes Yes No No
253 Check GICv2m MSI to SPI Generation L1 Appendix I.6 No Yes Yes Yes Yes No No
254 Check GICv2m SPI allocated to MSI Ctrl L1 Appendix I.5 No Yes Yes Yes Yes No No
276 Check number of ITS blocks in a group L1 ITS_01 Yes Yes Yes Yes Yes No No
277 Check ITS block association with group L1 ITS_02 Yes Yes Yes Yes Yes No No
278 Check uniqueness of StreamID L1 ITS_DEV_2 Yes Yes Yes Yes Yes No No
279 Check Device's ReqID-DeviceID-StreamID L1 ITS_DEV_7, ITS_DEV_8 Yes Yes Yes Yes Yes No No
301 All SMMUs have same Arch Revision L1 B_SMMU_01 Yes Yes Yes Yes Yes No No
302 Check SMMU Granule Support L1 B_SMMU_02 Yes Yes Yes Yes Yes No No
303 Check SMMU Large Physical Addr Support L1 B_SMMU_06 Yes Yes Yes Yes Yes No No
304 Check SMMU S-EL2 & stage1 support L1 B_SMMU_08 Yes Yes Yes Yes Yes No No
352 Check SMMU S-EL2 & stage2 support L1 B_SMMU_16, B_SMMU_17, B_SMMU_18 Yes Yes Yes Yes Yes No No
353 SMMUv2 unique intr per ctxt bank L1 B_SMMU_19 Yes Yes Yes Yes Yes No No
354 SMMUv3 Integration compliance L1 B_SMMU_21, SMMU_01 Yes Yes Yes Yes Yes No No
401 Check Counter Frequency L1 B_TIME_01, B_TIME_02 Yes Yes Yes Yes Yes No No
402 SYS Timer if PE Timer not ON L1 B_TIME_06 Yes Yes Yes Yes Yes No No
403 Memory mapped timer check L1 B_TIME_07, B_TIME_10 Yes Yes Yes Yes Yes No No
404 Generate Mem Mapped SYS Timer Intr L1 B_TIME_08 Yes Yes Yes Yes Yes No No
405 Restore PE timer on PE wake up L1 B_TIME_09 Yes Yes Yes Yes Yes No No
501 Wake from EL1 PHY Timer Int L1 B_WAK_01 - B_WAK_07, B_WAK_10, B_WAK_11 Yes Yes Yes Yes Yes No No
502 Wake from EL1 VIR Timer Int L1 B_WAK_01 - B_WAK_07, B_WAK_10, B_WAK_11 Yes Yes Yes Yes Yes No No
503 Wake from EL2 PHY Timer Int L1 B_WAK_01 - B_WAK_07, B_WAK_10, B_WAK_11 Yes Yes Yes Yes Yes No No
504 Wake from Watchdog WS0 Int L1 B_WAK_01 - B_WAK_07, B_WAK_10, B_WAK_11 Yes Yes Yes Yes Yes No No
505 Wake from System Timer Int L1 B_WAK_01 - B_WAK_07, B_WAK_10, B_WAK_11 Yes Yes Yes Yes Yes No No
601 USB CTRL Interface L1 B_PER_01, B_PER_02 Yes Yes Yes Yes Yes No No
602 Check SATA CTRL Interface L1 B_PER_03 Yes Yes Yes Yes Yes No No
603 Check Arm BSA UART register offsets L1 B_PER_05, S_L3PR_01 Yes Yes Yes Yes Yes No No
604 Check Arm GENERIC UART Interrupt L1 B_PER_06, B_PER_07 Yes Yes Yes Yes Yes No No
605 Memory Attribute of DMA L1 B_PER_09, B_PER_10 Yes Yes Yes Yes# Yes Yes No
606 16550 compatible UART L1 B_PER_05, S_L3PR_01 Yes Yes Yes Yes Yes No No
701 Non Secure Watchdog Access L1 B_WD_01, B_WD_02, S_L3WD_01 Yes Yes Yes Yes Yes No No
702 Check Watchdog WS0 interrupt L1 B_WD_03, S_L3WD_01 Yes Yes Yes Yes Yes No No
801 Check ECAM Presence L1 PCI_IN_01 Yes Yes Yes Yes Yes No No
802 PE - ECAM Region accessibility check L1 PCI_IN_02 Yes Yes Yes Yes Yes No No
803 All EP/Sw under RP in same ECAM Region L1 PCI_IN_04 Yes Yes Yes Yes Yes No No
804 Check RootPort NP Memory Access L1 PCI_IN_13 No No No Yes# Yes No No
805 Check RootPort P Memory Access L1 PCI_IN_13 No No No Yes# Yes No No
806 Legacy int must be SPI & lvl-sensitive L1 PCI_LI_01, PCI_LI_03 Yes Yes Yes Yes Yes No No
808 Check all 1's for out of range L1 PCI_IN_16 Yes Yes Yes Yes Yes No No
809 Vendor specfic data are PCIe compliant L1 PCI_IN_20 Yes Yes Yes Yes Yes No No
811 Check RP Byte Enable Rules L1 PCI_IN_18 Yes Yes Yes Yes Yes No No
817 Check Direct Transl P2P Support L1 PCI_PP_05 Yes Yes Yes Yes Yes No No
818 Check RP Adv Error Report L1 PCI_PP_05 Yes Yes Yes Yes Yes No No
819 RP must suprt ACS if P2P Txn are allow L1 PCI_PP_03 Yes Yes Yes Yes Yes No No
820 Type 0/1 common config rule L1 PCI_IN_05, PCI_IN_19 Yes Yes Yes Yes Yes No No
821 Type 0 config header rules L1 B_PER_12 Yes Yes Yes Yes Yes No No
822 Check Type 1 config header rules L1 PCI_IN_05, PCI_IN_19 Yes Yes Yes Yes Yes No No
824 Device capabilities reg rule L1 PCI_IN_05 Yes Yes Yes Yes Yes No No
825 Device Control register rule L1 PCI_IN_05 Yes Yes Yes Yes Yes No No
826 Device cap 2 register rules L1 PCI_IN_05 Yes Yes Yes Yes Yes No No
830 Check Cmd Reg memory space enable L1 PCI_IN_19 Yes Yes Yes Yes Yes No No
831 Check Type0/1 BIST Register rule L1 PCI_IN_19 Yes Yes Yes Yes Yes No No
832 Check HDR CapPtr Register rule L1 PCI_IN_19 Yes Yes Yes Yes Yes No No
833 Check Max payload size supported L1 PCI_IN_05 Yes Yes Yes Yes Yes No No
835 Check Function level reset L1 PCI_SM_02 Yes Yes Yes Yes Yes No No
836 Check ARI forwarding enable rule L1 PCI_IN_17 Yes Yes Yes Yes Yes No No
837 Check Config Txn for RP in HB L1 PCI_IN_12 Yes Yes Yes Yes Yes No No
838 Check all RP in HB is in same ECAM L1 PCI_IN_03 Yes Yes Yes Yes Yes No No
839 Check MSI support for PCIe dev L1 PCI_MSI_01 Yes Yes Yes Yes Yes No No
842 PASID support atleast 16 bits L1 PCI_PAS_1 Yes Yes Yes Yes Yes No No
861 PCIe Unaligned access L1 PCI_MM_01, PCI_MM_02, PCI_MM_03 Yes Yes Yes Yes# Yes Yes No
862 No extra address translation L1 PCI_MM_05, PCI_MM_06, PCI_MM_07 Yes Yes Yes Yes# Yes Yes No
863 PCI legacy intr SPI ID unique L1 PCI_LI_02 Yes Yes Yes Yes# Yes Yes No
864 Check MSI=X vectors uniqueness L1 PCI_MSI_2 Yes Yes Yes Yes# Yes Yes No
901 Check P2P ACS Functionality L1 PCI_PP_04 No No No Yes Yes No Yes
902 Check ACS Redirect Req Valid L1 PCI_PP_04 No No No Yes Yes No Yes
903 Arrival order Check L1 PCI_IC_15 No No No Yes Yes No Yes
904 MSI-X triggers intr with unique ID L1 PCI_MSI_2, ITS_DEV_6 No No No Yes Yes No Yes
905 Generate PASID transactions L1 PCI_PAS_1, RE_SMU_4, IE_SMU_3 No No No Yes Yes No Yes
906 Generate PCIe legacy interrupt L1 PCI_LI_02 No No No Yes Yes No Yes
907 Check PCIe I/O Coherency L1 PCI_IC_11, PCI_IC_13, PCI_IC_16, PCI_IC_17, PCI_IC_18 No No No Yes Yes No Yes
908 Check PCIe Software Coherency L1 PCI_IC_14, RE_ORD_4, IE_ORD_4 No No No Yes Yes No Yes
910 Check RP Sec Bus transaction are TYPE0 L1 PCI_IN_11 No No No Yes Yes No Yes
911 MSI to Any ITS Blk in assigned group L1 ITS_03, ITS_04, ITS_06, ITS_07, ITS_08, ITS_DEV_1, ITS_DEV_5 No No No Yes Yes No Yes
912 MSI to ITS Blk outside assigned group L1 ITS_05 No No No Yes Yes No Yes
913 MSI originating from different master L1 ITS_DEV_4 No No No Yes Yes No Yes
914 P2P transactions must not deadlock L1 PCI_PP_02 No No No Yes Yes No Yes
915 Check ARI forwarding enable rule L1 PCI_IN_17 No No No Yes Yes No Yes
916 PCIe Memory access check L1 PCI_MM_01, PCI_MM_02, PCI_MM_03 No No No Yes Yes No Yes
917 Check BME functionality of RP L1 IE_REG_3, PCI_IN_05 No No No Yes Yes No Yes

For running tests on a bare-metal environment, integration of ACS with platform boot code is required. See arm BSA Bare-metal User Guide