refactor timer support into infra layer and update generic timer access

avinaw01-arm · chetan-rathore · commit 08996a39efd0 · 2026-06-24T15:10:16.000+05:30
- split timer infrastructure helpers into acs_timer_infra
  - move generic timer register APIs into acs_timer.h
  - add EL2/VHE-aware timer register read/write handling
  - program EL1/EL2 timers through CVAL instead of TVAL
  - update build files, headers, and timer/ETE call sites to use the new interfaces

Signed-off-by: Avi Nawal &lt;Avi.Nawal@arm.com&gt;
Change-Id: Idb3bb598cc77311005217199592501f098f53faf
diff --git a/test_pool/ete/ete003.c b/test_pool/ete/ete003.c
@@ -19,7 +19,7 @@
 #include "acs_pe.h"
 #include "val_interface.h"
 #include "acs_memory.h"
-#include "acs_timer_support.h"
+#include "acs_timer.h"
 #include "acs_ete.h"
 
 #define TEST_NUM   (ACS_ETE_TEST_NUM_BASE + 3)
diff --git a/test_pool/ete/ete004.c b/test_pool/ete/ete004.c
@@ -17,7 +17,7 @@
 
 #include "acs_val.h"
 #include "acs_pe.h"
-#include "acs_timer_support.h"
+#include "acs_timer.h"
 #include "acs_ete.h"
 #include "val_interface.h"
 #include "acs_memory.h"
diff --git a/test_pool/timer/t001.c b/test_pool/timer/t001.c
@@ -16,7 +16,7 @@
  **/
 
 #include "acs_val.h"
-#include "acs_timer.h"
+#include "acs_timer_infra.h"
 
 #define TEST_NUM   (ACS_TIMER_TEST_NUM_BASE + 1)
 #define TEST_RULE  "B_TIME_01"
diff --git a/test_pool/timer/t002.c b/test_pool/timer/t002.c
@@ -17,7 +17,7 @@
 
 #include "acs_val.h"
 #include "val_interface.h"
-#include "acs_timer.h"
+#include "acs_timer_infra.h"
 
 #define TEST_NUM   (ACS_TIMER_TEST_NUM_BASE + 2)
 #define TEST_RULE  "B_TIME_06"
diff --git a/test_pool/timer/t003.c b/test_pool/timer/t003.c
@@ -16,7 +16,7 @@
  **/
 #include "acs_val.h"
 #include "val_interface.h"
-#include "acs_timer.h"
+#include "acs_timer_infra.h"
 
 #define TEST_NUM   (ACS_TIMER_TEST_NUM_BASE + 3)
 #define TEST_RULE  "B_TIME_07"
diff --git a/test_pool/timer/t004.c b/test_pool/timer/t004.c
@@ -17,7 +17,7 @@
 #include "acs_val.h"
 #include "acs_gic.h"
 #include "gic_v3.h"
-#include "acs_timer.h"
+#include "acs_timer_infra.h"
 #include "acs_wakeup.h"
 #include "val_interface.h"
 
diff --git a/test_pool/timer/t005.c b/test_pool/timer/t005.c
@@ -17,7 +17,7 @@
 
 #include "acs_val.h"
 #include "val_interface.h"
-#include "acs_timer.h"
+#include "acs_timer_infra.h"
 #include "acs_pe.h"
 
 #define TEST_NUM   (ACS_TIMER_TEST_NUM_BASE + 5)
diff --git a/test_pool/timer/t006.c b/test_pool/timer/t006.c
@@ -17,7 +17,7 @@
 
 #include "acs_val.h"
 #include "acs_timer.h"
-#include "acs_timer_support.h"
+#include "acs_timer_infra.h"
 
 #define TEST_NUM   (ACS_TIMER_TEST_NUM_BASE + 6)
 #define TEST_RULE  "S_L5TI_01"
diff --git a/test_pool/timer/t008.c b/test_pool/timer/t008.c
@@ -16,8 +16,8 @@
 **/
 
 #include "acs_val.h"
+#include "acs_timer_infra.h"
 #include "acs_timer.h"
-#include "acs_timer_support.h"
 #include "acs_pe.h"
 #include "val_interface.h"
 
diff --git a/val/SbsaValNistLib.inf b/val/SbsaValNistLib.inf
@@ -43,8 +43,8 @@
   src/acs_mmu.c
   src/acs_smmu.c
   src/acs_test_infra.c
+  src/acs_timer_infra.c
   src/acs_timer.c
-  src/acs_timer_support.c
   src/acs_wd.c
   src/acs_wakeup.c
   src/acs_peripherals.c
diff --git a/val/ValLib.inf b/val/ValLib.inf
@@ -43,8 +43,8 @@
   src/acs_mmu.c
   src/acs_smmu.c
   src/acs_test_infra.c
+  src/acs_timer_infra.c
   src/acs_timer.c
-  src/acs_timer_support.c
   src/acs_wd.c
   src/acs_wakeup.c
   src/acs_peripherals.c
diff --git a/val/ValLibRB.inf b/val/ValLibRB.inf
@@ -45,8 +45,8 @@
   src/acs_mmu.c
   src/acs_smmu.c
   src/acs_test_infra.c
+  src/acs_timer_infra.c
   src/acs_timer.c
-  src/acs_timer_support.c
   src/acs_wd.c
   src/acs_wakeup.c
   src/acs_peripherals.c
diff --git a/val/include/acs_timer.h b/val/include/acs_timer.h
@@ -1,6 +1,5 @@
-
 /** @file
- * Copyright (c) 2016-2018, 2021, 2024-2026, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -19,35 +18,61 @@
 #ifndef __ACS_TIMER_H__
 #define __ACS_TIMER_H__
 
+#include "val_sysreg_timer.h"
+#include "acs_timer_infra.h"
+
 #define ARM_ARCH_TIMER_ENABLE           (1 << 0)
 #define ARM_ARCH_TIMER_IMASK            (1 << 1)
 #define ARM_ARCH_TIMER_ISTATUS          (1 << 2)
 
-/* CNTCTLBase register offset */
-#define CNTTIDR          0x8
-#define CNTACR           0x40
-
-/* CNTBaseN register offset*/
-#define CNTPCT_LOWER     0x00
-#define CNTPCT_HIGHER    0x04
-#define CNTVCT_LOWER     0x08
-#define CNTVCT_HIGHER    0x0C
-#define CNTBaseN_CNTFRQ  0x10
-#define CNTP_CVAL_LOWER  0x20
-#define CNTP_CVAL_HIGHER 0x24
-#define CNTP_TVAL        0x28
-#define CNTP_CTL         0x2C
-#define COUNTER_ID       0xFD0
-
-#define MICRO_SECONDS    1000000
-#define MAX_WAKEUP_TIMEOUT 5
-
-uint32_t t001_entry(uint32_t num_pe);
-uint32_t t002_entry(uint32_t num_pe);
-uint32_t t003_entry(uint32_t num_pe);
-uint32_t t004_entry(uint32_t num_pe);
-uint32_t t005_entry(uint32_t num_pe);
-uint32_t t006_entry(uint32_t num_pe);
-uint32_t t008_entry(uint32_t num_pe);
-uint32_t t009_entry(uint32_t num_pe);
+typedef enum {
+  CntFrq = 0,
+  CntPct,
+  CntPctSS,
+  CntkCtl,
+  CntpTval,
+  CntpCtl,
+  CntvTval,
+  CntvCtl,
+  CntvCt,
+  CntVctSS,
+  CntpCval,
+  CntvCval,
+  CntvOff,
+  CnthCtl,
+  CnthpTval,
+  CnthpCtl,
+  CnthpCval,
+  CnthvTval,
+  CnthvCtl,
+  CnthvCval,
+  RegMaximum
+} ARM_ARCH_TIMER_REGS;
+
+
+uint64_t
+ArmArchTimerReadReg (
+  ARM_ARCH_TIMER_REGS   Reg
+  );
+
+
+void
+ArmArchTimerWriteReg (
+    ARM_ARCH_TIMER_REGS   Reg,
+    uint64_t              *data_buf
+  );
+
+void
+ArmWriteCntFrq (
+  uint64_t   FreqInHz
+  );
+
+void ArmGenericTimerEnableTimer (ARM_ARCH_TIMER_REGS reg);
+void ArmGenericTimerDisableTimer (ARM_ARCH_TIMER_REGS reg);
+
+void val_timer_set_phy_el1(uint32_t timeout);
+void val_timer_set_vir_el1(uint32_t timeout);
+void val_timer_set_phy_el2(uint32_t timeout);
+void val_timer_set_vir_el2(uint32_t timeout);
+
 #endif // __ACS_TIMER_H__
diff --git a/val/include/acs_timer_infra.h b/val/include/acs_timer_infra.h
@@ -0,0 +1,53 @@
+/** @file
+ * Copyright (c) 2026, Arm Limited or its affiliates. All rights reserved.
+ * SPDX-License-Identifier : Apache-2.0
+
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+**/
+
+#ifndef __ACS_TIMER_INFRA_H__
+#define __ACS_TIMER_INFRA_H__
+
+#define ARM_ARCH_TIMER_ENABLE           (1 << 0)
+#define ARM_ARCH_TIMER_IMASK            (1 << 1)
+#define ARM_ARCH_TIMER_ISTATUS          (1 << 2)
+
+/* CNTCTLBase register offset */
+#define CNTTIDR          0x8
+#define CNTACR           0x40
+
+/* CNTBaseN register offset*/
+#define CNTPCT_LOWER     0x00
+#define CNTPCT_HIGHER    0x04
+#define CNTVCT_LOWER     0x08
+#define CNTVCT_HIGHER    0x0C
+#define CNTBaseN_CNTFRQ  0x10
+#define CNTP_CVAL_LOWER  0x20
+#define CNTP_CVAL_HIGHER 0x24
+#define CNTP_TVAL        0x28
+#define CNTP_CTL         0x2C
+#define COUNTER_ID       0xFD0
+
+#define MICRO_SECONDS    1000000
+#define MAX_WAKEUP_TIMEOUT 5
+
+uint32_t t001_entry(uint32_t num_pe);
+uint32_t t002_entry(uint32_t num_pe);
+uint32_t t003_entry(uint32_t num_pe);
+uint32_t t004_entry(uint32_t num_pe);
+uint32_t t005_entry(uint32_t num_pe);
+uint32_t t006_entry(uint32_t num_pe);
+uint32_t t007_entry(uint32_t num_pe);
+uint32_t t008_entry(uint32_t num_pe);
+uint32_t t009_entry(uint32_t num_pe);
+#endif // __ACS_TIMER_INFRA_H__
diff --git a/val/include/acs_timer_support.h b/val/include/acs_timer_support.h
diff --git a/val/include/val_interface.h b/val/include/val_interface.h
@@ -25,6 +25,7 @@
 #include "acs_execution_policy.h"
 #include "val_status.h"
 #include "val_libc.h"
+#include "acs_timer.h"
 
 #define ACS_STATUS_ERR       0xEDCB1234  //some impropable value?
 #define ACS_STATUS_NIST_PASS 0x1
@@ -242,14 +243,10 @@ typedef enum {
 #define BSA_TIMER_FLAG_ALWAYS_ON 0x4
 void     val_timer_create_info_table(uint64_t *timer_info_table);
 void     val_timer_free_info_table(void);
-void     val_timer_set_phy_el1(uint32_t timeout);
-void     val_timer_set_vir_el1(uint32_t timeout);
 void     val_platform_timer_get_entry_index(uint64_t instance, uint32_t *block, uint32_t *index);
 uint64_t val_timer_get_info(TIMER_INFO_e info_type, uint64_t instance);
 uint64_t val_get_phy_el2_timer_count(void);
 uint32_t val_bsa_timer_execute_tests(uint32_t num_pe, uint32_t *g_sw_view);
-void     val_timer_set_phy_el2(uint32_t timeout);
-void     val_timer_set_vir_el2(uint32_t timeout);
 void     val_timer_set_system_timer(addr_t cnt_base_n, uint32_t timeout);
 void     val_timer_disable_system_timer(addr_t cnt_base_n);
 uint32_t val_timer_skip_if_cntbase_access_not_allowed(uint64_t index);
diff --git a/val/include/val_sysreg_timer.h b/val/include/val_sysreg_timer.h
@@ -17,6 +17,7 @@ SYSREG_RW_FUNCS(cnthp_tval_el2)
 SYSREG_RW_FUNCS(cnthv_ctl_el2)
 SYSREG_RW_FUNCS(cnthv_tval_el2)
 SYSREG_RW_FUNCS(cnthp_cval_el2)
+SYSREG_RW_FUNCS(cnthv_cval_el2)
 SYSREG_RW_FUNCS(cntps_ctl_el1)
 SYSREG_RW_FUNCS(cntps_tval_el1)
 SYSREG_RW_FUNCS(cntps_cval_el1)
diff --git a/val/src/acs_pe.c b/val/src/acs_pe.c
@@ -24,7 +24,7 @@
 #include "val_interface.h"
 #include "val_sysreg_mpam.h"
 #include "acs_std_smc.h"
-#include "acs_timer_support.h"
+#include "acs_timer.h"
 
 /**
   @brief   Pointer to the memory location of the PE Information table
diff --git a/val/src/acs_timer.c b/val/src/acs_timer.c
diff --git a/val/src/acs_timer_infra.c b/val/src/acs_timer_infra.c
diff --git a/val/src/acs_timer_support.c b/val/src/acs_timer_support.c
diff --git a/val/src/acs_wd.c b/val/src/acs_wd.c
diff --git a/val/src/bsa_execute_test.c b/val/src/bsa_execute_test.c
diff --git a/val/src/pc_bsa_execute_test.c b/val/src/pc_bsa_execute_test.c
diff --git a/val/src/sbsa_execute_test.c b/val/src/sbsa_execute_test.c
