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Sujana-MSujana-M
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fix(pcie): skip non-prefetchable BARs in P094 flow
- add BAR_MEM macro to detect non-prefetchable BAR type - skip NP BARs and check only for Prefetch bars to avoid any side effects - Mask the last 4 bits of the BAR value as it points to the attributes. - Skip cndition to be verified first before checking the warn condition. - Map Prefetch bar of base+32MB as most platforms map below 32MB to mapped to control registers, lookup tables, or routing tables. - The endpoint check is incorrectly checked as a result only first 2 BARS were checked. Updated to check the right return type. - When first BAR is 0, skipping to next BDF, instead of next bar, updated the changes accordingly to check for next bdf Signed-off-by: Sujana M <sujana.murali@arm.com> Change-Id: Ieaa6609814cd25efb6495d8b5a77d4da73eabfea
1 parent 0ce7220 commit 902a19c

4 files changed

Lines changed: 74 additions & 69 deletions

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‎test_pool/pcie/p045.c‎

Lines changed: 29 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -108,48 +108,46 @@ payload(void)
108108
continue;
109109
}
110110

111+
val_print(DEBUG, "\n BDF under check %.6x", bdf);
112+
val_pcie_read_cfg(bdf, TYPE01_RIDR, &reg_value);
113+
val_print(DEBUG, "\n Class code is 0x%x", reg_value);
114+
base_cc = reg_value >> TYPE01_BCC_SHIFT;
115+
116+
if (g_pcie_skip_dp_nic_ms &&
117+
((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC)
118+
|| (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) {
119+
val_print(DEBUG, "\n Skipping BDF 0x%x", bdf);
120+
tbl_index++;
121+
goto next_bdf;
122+
}
123+
111124
/* Configure the max BAR offset */
112125
dev_type = val_pcie_get_device_type(bdf);
113-
if (dev_type == 0)
126+
if (dev_type == 1)
114127
max_bar_offset = BAR_TYPE_0_MAX_OFFSET;
115128
else
116129
max_bar_offset = BAR_TYPE_1_MAX_OFFSET;
117130

118131
offset = BAR0_OFFSET;
119132

120-
val_print(DEBUG, "\n BDF under check %.6x", bdf);
121-
122133
while (offset <= max_bar_offset) {
123134
val_pcie_read_cfg(bdf, offset, &bar_value);
124-
val_print(DEBUG, "\n The BAR value of bdf %.6x", bdf);
135+
val_print(DEBUG, "\n The BAR value at offset %x", offset);
125136
val_print(DEBUG, " is %x ", bar_value);
126137
base = 0;
127138

128139
if (bar_value == 0)
129140
{
130141
/** This BAR is not implemented **/
131142
val_print(DEBUG, "\n BAR is not implemented for BDF 0x%x", bdf);
132-
tbl_index++;
133-
goto next_bdf;
143+
goto next_bar;
134144
}
135145

136146
/* Skip for IO address space */
137147
if (bar_value & 0x1) {
138148
val_print(DEBUG, "\n BAR is used for IO address space request");
139149
val_print(DEBUG, " for BDF 0x%x", bdf);
140-
tbl_index++;
141-
goto next_bdf;
142-
}
143-
144-
val_pcie_read_cfg(bdf, TYPE01_RIDR, &reg_value);
145-
val_print(DEBUG, "\n Class code is 0x%x", reg_value);
146-
base_cc = reg_value >> TYPE01_BCC_SHIFT;
147-
if (g_pcie_skip_dp_nic_ms &&
148-
((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC)
149-
|| (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) {
150-
val_print(DEBUG, "\n Skipping BDF as 0x%x", bdf);
151-
tbl_index++;
152-
goto next_bdf;
150+
goto next_bar;
153151
}
154152

155153
if (BAR_REG(bar_value) == BAR_64_BIT)
@@ -174,7 +172,7 @@ payload(void)
174172
/* Restore the original BAR value */
175173
val_pcie_write_cfg(bdf, offset + 4, bar_value_1);
176174
val_pcie_write_cfg(bdf, offset, bar_value);
177-
base = (base << 32) | bar_value;
175+
base = (base << 32) | (bar_value & BAR_MASK);
178176
}
179177

180178
else {
@@ -191,10 +189,11 @@ payload(void)
191189

192190
/* Restore the original BAR value */
193191
val_pcie_write_cfg(bdf, offset, bar_value);
194-
base = bar_value;
192+
base = bar_value & BAR_MASK;
195193
}
196194

197195
val_print(DEBUG, "\n BAR size is %x", bar_size);
196+
val_print(DEBUG, "\n BAR base is 0x%llx", base);
198197

199198
/* Check if bar supports the remap size */
200199
if (bar_size < 1024) {
@@ -218,11 +217,11 @@ payload(void)
218217

219218
/* Handle unimplemented PAL -> Report WARN */
220219
if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) {
221-
test_abort = 1;
222-
break;
220+
goto test_status;
223221
}
224222
else if (status) {
225-
val_print(ERROR, "\n Failed in ioremap with status %x", status);
223+
val_print(ERROR,
224+
"\n pal_memory_ioremap failed, status: 0x%x", status);
226225
test_fail++;
227226
val_set_status(index, RESULT_FAIL(test_fail));
228227
goto next_bar;
@@ -257,21 +256,18 @@ payload(void)
257256
if (msa_en)
258257
val_pcie_disable_msa(bdf);
259258
}
260-
261-
if (test_abort == 1)
262-
break;
263259
}
264260

265-
if (test_warn) {
266-
val_set_status(index, RESULT_WARNING(0));
267-
return;
268-
} else if (test_skip)
261+
test_status:
262+
if (test_skip)
269263
val_set_status(index, RESULT_SKIP(1));
270-
else if (test_fail)
264+
else if (test_warn) {
265+
val_set_status(index, RESULT_WARNING(1));
266+
} else if (test_fail)
271267
val_set_status(index, RESULT_FAIL(test_fail));
272268
else
273269
val_set_status(index, RESULT_PASS);
274-
270+
return;
275271
}
276272

277273
uint32_t

‎test_pool/pcie/p094.c‎

Lines changed: 43 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,6 @@ payload(void)
6868
uint32_t test_skip = 1;
6969
uint32_t test_warn = 1;
7070
uint32_t test_fail = 0;
71-
uint32_t test_abort = 0;
7271
uint64_t offset;
7372
uint64_t base;
7473
pcie_device_bdf_table *bdf_tbl_ptr;
@@ -109,48 +108,52 @@ payload(void)
109108
continue;
110109
}
111110

111+
val_print(DEBUG, "\n BDF under check %.6x", bdf);
112+
val_pcie_read_cfg(bdf, TYPE01_RIDR, &reg_value);
113+
val_print(DEBUG, "\n Class code is 0x%x", reg_value);
114+
base_cc = reg_value >> TYPE01_BCC_SHIFT;
115+
116+
if (g_pcie_skip_dp_nic_ms &&
117+
((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC)
118+
|| (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) {
119+
val_print(DEBUG, "\n Skipping BDF 0x%x", bdf);
120+
tbl_index++;
121+
goto next_bdf;
122+
}
123+
112124
/* Configure the max BAR offset */
113125
dev_type = val_pcie_get_device_type(bdf);
114-
if (dev_type == 0)
126+
if (dev_type == 1)
115127
max_bar_offset = BAR_TYPE_0_MAX_OFFSET;
116128
else
117129
max_bar_offset = BAR_TYPE_1_MAX_OFFSET;
118130

119131
offset = BAR0_OFFSET;
120132

121-
val_print(DEBUG, "\n BDF under check %.6x", bdf);
122-
123133
while (offset <= max_bar_offset) {
124134
val_pcie_read_cfg(bdf, offset, &bar_value);
125-
val_print(DEBUG, "\n The BAR value of bdf %.6x", bdf);
126-
val_print(DEBUG, " is %x ", bar_value);
135+
val_print(DEBUG, "\n The BAR value at offset %x", offset);
136+
val_print(DEBUG, " is %x", bar_value);
127137
base = 0;
128138

129139
if (bar_value == 0)
130140
{
131141
/** This BAR is not implemented **/
132142
val_print(DEBUG, "\n BAR is not implemented for BDF 0x%x", bdf);
133-
tbl_index++;
134-
goto next_bdf;
143+
goto next_bar;
135144
}
136145

137146
/* Skip for IO address space */
138147
if (bar_value & BAR_VALUE_IO_MASK) {
139148
val_print(DEBUG, "\n BAR is used for IO address space request");
140-
val_print(DEBUG, " for BDF 0x%x", bdf);
141-
tbl_index++;
142-
goto next_bdf;
149+
goto next_bar;
143150
}
144151

145-
val_pcie_read_cfg(bdf, TYPE01_RIDR, &reg_value);
146-
val_print(DEBUG, "\n Class code is 0x%x", reg_value);
147-
base_cc = reg_value >> TYPE01_BCC_SHIFT;
148-
if (g_pcie_skip_dp_nic_ms &&
149-
((base_cc == UNCLAS_CC) || (base_cc == CNTRL_CC)
150-
|| (base_cc == DP_CNTRL_CC) || (base_cc == MAS_CC))) {
151-
val_print(DEBUG, "\n Skipping BDF as 0x%x", bdf);
152-
tbl_index++;
153-
goto next_bdf;
152+
/* Skip for NP BAR to avoid side effects */
153+
if (BAR_MEM(bar_value) == BAR_NP_TYPE) {
154+
val_print(DEBUG, "\n BAR is of type Non-Prefetch");
155+
val_print(DEBUG, " at offset 0x%x", offset);
156+
goto next_bar;
154157
}
155158

156159
if (BAR_REG(bar_value) == BAR_64_BIT)
@@ -175,7 +178,7 @@ payload(void)
175178
/* Restore the original BAR value */
176179
val_pcie_write_cfg(bdf, offset + 4, bar_value_1);
177180
val_pcie_write_cfg(bdf, offset, bar_value);
178-
base = (base << 32) | bar_value;
181+
base = (base << 32) | (bar_value & BAR_MASK);
179182
}
180183

181184
else {
@@ -192,15 +195,20 @@ payload(void)
192195

193196
/* Restore the original BAR value */
194197
val_pcie_write_cfg(bdf, offset, bar_value);
195-
base = bar_value;
198+
base = bar_value & BAR_MASK;
196199
}
197200

198201
val_print(DEBUG, "\n BAR size is %x", bar_size);
199202
val_print(DEBUG, "\n BAR base is 0x%llx", base);
200203

201-
/* Check if bar supports the remap size */
202-
if (bar_size < 1024) {
203-
val_print(ERROR, "\n Bar size less than remap requested size");
204+
/* Check if bar supports the remap size
205+
* Prefetch memory of size less than 32MB is
206+
* is mapped to control register/lookup tables
207+
* in certain platforms. Hence skipping if size
208+
* is less than 32MB
209+
*/
210+
if (bar_size < SIZE_32M) {
211+
val_print(DEBUG, "\n Bar size less than 32MB. Skipping this BAR");
204212
goto next_bar;
205213
}
206214

@@ -213,13 +221,15 @@ payload(void)
213221

214222
test_skip = 0;
215223

224+
base = base + SIZE_32M;
225+
val_print(DEBUG, "\n BAR base accessed is 0x%llx", base);
226+
216227
/* Map the BARs to a NORMAL memory attribute. check unaligned access */
217228
status = val_memory_ioremap((void *)base, 1024, NORMAL_NC, (void **)&baseptr);
218229

219230
/* Handle unimplemented PAL -> Report WARN */
220231
if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) {
221-
test_abort = 1;
222-
break;
232+
goto test_status;
223233
}
224234
else if (status)
225235
{
@@ -263,21 +273,18 @@ payload(void)
263273
if (msa_en)
264274
val_pcie_disable_msa(bdf);
265275
}
266-
267-
if (test_abort == 1)
268-
break;
269276
}
270277

271-
if (test_warn) {
278+
test_status:
279+
if (test_skip)
280+
val_set_status(index, RESULT_SKIP(1));
281+
else if (test_warn) {
272282
val_set_status(index, RESULT_WARNING(1));
273-
return;
274-
} else if (test_skip)
275-
val_set_status(index, RESULT_FAIL(1));
276-
else if (test_fail)
283+
} else if (test_fail)
277284
val_set_status(index, RESULT_FAIL(test_fail));
278285
else
279286
val_set_status(index, RESULT_PASS);
280-
287+
return;
281288
}
282289

283290
uint32_t

‎val/include/acs_pcie_spec.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,7 @@
140140
#define BAR_VALUE_PREFETCH_MASK 0x8
141141
#define BAR_VALUE_IO_MASK 0x1
142142
#define BAR_REG(bar_reg_value) ((bar_reg_value >> 2) & 0x1)
143+
#define BAR_MEM(bar_reg_value) ((bar_reg_value & 0xF) >> 3)
143144

144145
#define TYPE0_MAX_BARS 6
145146
#define TYPE1_MAX_BARS 2

‎val/include/val_interface.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -771,6 +771,7 @@ uint32_t dl012_entry(uint32_t num_pe);
771771
#define SIZE_1K 1024ULL
772772
#define SIZE_16K 4 * SIZE_4K
773773
#define SIZE_1M SIZE_1K * SIZE_1K
774+
#define SIZE_32M 32 * SIZE_1M
774775
#define SIZE_1G SIZE_1M * SIZE_1K
775776

776777
#define SOFTLIMIT_DIS 0x0

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