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enhancement(pmu): add node_index to PMU event info
- Extend pal_pmu_get_event_info to use node_index for more granular event ID resolution across PMU nodes. - Update event_list entries, signatures, and related logic in PAL and VAL layers in UEFI and BM to support the enhancement. - Remove the hardcoded PMU `event_list` array from PAL implementations and instead declare it as a shared `PLATFORM_OVERRIDE_EVENT_DETAILS` array per platform (e.g., RDN2, RDV3, RDV3CFG1). This enables platform-specific configuration of PMU events. - Update `pal_pmu_get_event_info()` to use `node_index` for precise event ID lookup, supporting cases with multiple PMU nodes of the same type. - Delete unused `pal_pmu.h` from baremetal and unify the `event_details` struct definition across PAL layers. Signed-off-by: Sujana M <sujana.murali@arm.com> Change-Id: I37350362942878c8621809ae940999aab5ca3efe
1 parent 389aa1a commit b52b8ef

12 files changed

Lines changed: 265 additions & 144 deletions

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‎pal/baremetal/base/include/pal_pmu.h‎

Lines changed: 0 additions & 52 deletions
This file was deleted.

‎pal/baremetal/base/src/pal_pmu.c‎

Lines changed: 8 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -16,10 +16,10 @@
1616
**/
1717

1818
#include "platform_override_struct.h"
19-
#include "pal_pmu.h"
2019
#include "pal_common_support.h"
2120

2221
extern PLATFORM_OVERRIDE_PMU_INFO_TABLE platform_pmu_cfg;
22+
extern PLATFORM_OVERRIDE_EVENT_DETAILS event_list[];
2323

2424
/**
2525
@brief Display PMU info table details
@@ -98,61 +98,27 @@ pal_pmu_create_info_table(PMU_INFO_TABLE *PmuTable)
9898
}
9999
}
100100

101-
typedef struct{
102-
PMU_NODE_INFO_TYPE node_type;
103-
PMU_EVENT_TYPE_e event_desc;
104-
uint32_t event_id;
105-
}event_details;
106-
107-
/* Array containing the details of implementation defined system PMU events */
108-
event_details event_list[] = {
109-
{PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
110-
{PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
111-
{PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
112-
{PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
113-
{PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
114-
{PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
115-
{PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
116-
{PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
117-
{PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
118-
{PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
119-
{PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
120-
{PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
121-
{PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
122-
{PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
123-
{PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
124-
{PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
125-
{PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
126-
{PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
127-
{PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
128-
{PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
129-
{PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
130-
{PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
131-
{PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
132-
{PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
133-
{PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
134-
{PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
135-
{PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID},
136-
{PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID}
137-
};
138-
139101
/**
140102
@brief This API returns the event ID to be filled into PMEVTYPER register.
141103
Prerequisite - event_list array. This API should be called after
142104
filling the required event IDs into event_list array.
143105
106+
@param node_index - Index of PMU node.
144107
@param event_type - Type of the event.
145108
@param node_type - PMU Node type
146109
147110
@return Event ID
148111
149112
**/
150113
uint32_t
151-
pal_pmu_get_event_info(PMU_EVENT_TYPE_e event_type, PMU_NODE_INFO_TYPE node_type)
114+
pal_pmu_get_event_info(uint32_t node_index, PMU_EVENT_TYPE_e event_type,
115+
PMU_NODE_INFO_TYPE node_type)
152116
{
153-
uint32_t i=0;
154-
while (event_list[i].node_type != node_type || event_list[i].event_desc != event_type) {
117+
uint32_t i = 0;
118+
while (event_list[i].node_index != node_index || event_list[i].node_type != node_type ||
119+
event_list[i].event_desc != event_type) {
155120
i++;
156121
}
122+
157123
return event_list[i].event_id;
158124
}

‎pal/baremetal/target/RDN2/include/platform_override_struct.h‎

Lines changed: 36 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/** @file
2-
* Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved.
2+
* Copyright (c) 2024-2026, Arm Limited or its affiliates. All rights reserved.
33
* SPDX-License-Identifier : Apache-2.0
44
55
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -497,3 +497,38 @@ typedef struct {
497497
uint64_t tpm_base; /* TPM MMIO base address */
498498
uint64_t tpm_interface_type; /* StartMethod (6=TIS,7=CRB,...) */
499499
} PLATFORM_OVERRIDE_TPM2_INFO_TABLE;
500+
501+
typedef enum {
502+
PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */
503+
PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */
504+
PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */
505+
PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */
506+
PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */
507+
PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */
508+
PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */
509+
PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */
510+
PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */
511+
PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */
512+
PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */
513+
PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */
514+
PMU_EVENT_ALL_BW, /* All traffic bandwidth */
515+
PMU_EVENT_TRAFFIC_1, /* traffic type 1 */
516+
PMU_EVENT_TRAFFIC_2 /* traffic type 2 */
517+
} PMU_EVENT_TYPE_e;
518+
519+
typedef enum {
520+
PMU_NODE_MEM_CNTR,
521+
PMU_NODE_SMMU,
522+
PMU_NODE_PCIE_RC,
523+
PMU_NODE_ACPI_DEVICE,
524+
PMU_NODE_PE_CACHE
525+
} PMU_NODE_INFO_TYPE;
526+
527+
#define PMU_EVENT_INVALID 0xFFFFFFFF
528+
529+
typedef struct{
530+
uint32_t node_index;
531+
PMU_NODE_INFO_TYPE node_type;
532+
PMU_EVENT_TYPE_e event_desc;
533+
uint32_t event_id;
534+
} PLATFORM_OVERRIDE_EVENT_DETAILS;

‎pal/baremetal/target/RDN2/src/platform_cfg_fvp.c‎

Lines changed: 33 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/** @file
2-
* Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved.
2+
* Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved.
33
* SPDX-License-Identifier : Apache-2.0
44
55
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -1623,3 +1623,35 @@ PLATFORM_OVERRIDE_TPM2_INFO_TABLE platform_tpm2_cfg = {
16231623
.tpm_base = PLATFORM_TPM_BASE_ADDR,
16241624
.tpm_interface_type = PLATFORM_TPM_INTERFACE_TYPE,
16251625
};
1626+
1627+
/* Array containing the details of implementation defined system PMU events */
1628+
PLATFORM_OVERRIDE_EVENT_DETAILS event_list[] = {
1629+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
1630+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
1631+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
1632+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
1633+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
1634+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
1635+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
1636+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
1637+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
1638+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
1639+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
1640+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
1641+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
1642+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
1643+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
1644+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
1645+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
1646+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
1647+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
1648+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
1649+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
1650+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
1651+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
1652+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
1653+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
1654+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
1655+
{0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID},
1656+
{0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID}
1657+
};

‎pal/baremetal/target/RDV3/include/platform_override_struct.h‎

Lines changed: 36 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/** @file
2-
* Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved.
2+
* Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved.
33
* SPDX-License-Identifier : Apache-2.0
44
55
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -496,3 +496,38 @@ typedef struct {
496496
uint64_t tpm_base; /* TPM MMIO base address */
497497
uint64_t tpm_interface_type; /* StartMethod (6=TIS,7=CRB,...) */
498498
} PLATFORM_OVERRIDE_TPM2_INFO_TABLE;
499+
500+
typedef enum {
501+
PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */
502+
PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */
503+
PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */
504+
PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */
505+
PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */
506+
PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */
507+
PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */
508+
PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */
509+
PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */
510+
PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */
511+
PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */
512+
PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */
513+
PMU_EVENT_ALL_BW, /* All traffic bandwidth */
514+
PMU_EVENT_TRAFFIC_1, /* traffic type 1 */
515+
PMU_EVENT_TRAFFIC_2 /* traffic type 2 */
516+
} PMU_EVENT_TYPE_e;
517+
518+
typedef enum {
519+
PMU_NODE_MEM_CNTR,
520+
PMU_NODE_SMMU,
521+
PMU_NODE_PCIE_RC,
522+
PMU_NODE_ACPI_DEVICE,
523+
PMU_NODE_PE_CACHE
524+
} PMU_NODE_INFO_TYPE;
525+
526+
#define PMU_EVENT_INVALID 0xFFFFFFFF
527+
528+
typedef struct{
529+
uint32_t node_index;
530+
PMU_NODE_INFO_TYPE node_type;
531+
PMU_EVENT_TYPE_e event_desc;
532+
uint32_t event_id;
533+
} PLATFORM_OVERRIDE_EVENT_DETAILS;

‎pal/baremetal/target/RDV3/src/platform_cfg_fvp.c‎

Lines changed: 33 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/** @file
2-
* Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved.
2+
* Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved.
33
* SPDX-License-Identifier : Apache-2.0
44
55
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -1465,3 +1465,35 @@ PLATFORM_OVERRIDE_TPM2_INFO_TABLE platform_tpm2_cfg = {
14651465
.tpm_base = PLATFORM_TPM_BASE_ADDR,
14661466
.tpm_interface_type = PLATFORM_TPM_INTERFACE_TYPE,
14671467
};
1468+
1469+
/* Array containing the details of implementation defined system PMU events */
1470+
PLATFORM_OVERRIDE_EVENT_DETAILS event_list[] = {
1471+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
1472+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
1473+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
1474+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
1475+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
1476+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
1477+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
1478+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
1479+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
1480+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
1481+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
1482+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
1483+
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
1484+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
1485+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
1486+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
1487+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
1488+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
1489+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
1490+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
1491+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
1492+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
1493+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
1494+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
1495+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
1496+
{0, PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
1497+
{0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID},
1498+
{0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID}
1499+
};

‎pal/baremetal/target/RDV3CFG1/include/platform_override_struct.h‎

Lines changed: 36 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/** @file
2-
* Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved.
2+
* Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved.
33
* SPDX-License-Identifier : Apache-2.0
44
55
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -496,3 +496,38 @@ typedef struct {
496496
uint64_t tpm_base; /* TPM MMIO base address */
497497
uint64_t tpm_interface_type; /* StartMethod (6=TIS,7=CRB,...) */
498498
} PLATFORM_OVERRIDE_TPM2_INFO_TABLE;
499+
500+
typedef enum {
501+
PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */
502+
PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */
503+
PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */
504+
PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */
505+
PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */
506+
PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */
507+
PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */
508+
PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */
509+
PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */
510+
PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */
511+
PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */
512+
PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */
513+
PMU_EVENT_ALL_BW, /* All traffic bandwidth */
514+
PMU_EVENT_TRAFFIC_1, /* traffic type 1 */
515+
PMU_EVENT_TRAFFIC_2 /* traffic type 2 */
516+
} PMU_EVENT_TYPE_e;
517+
518+
typedef enum {
519+
PMU_NODE_MEM_CNTR,
520+
PMU_NODE_SMMU,
521+
PMU_NODE_PCIE_RC,
522+
PMU_NODE_ACPI_DEVICE,
523+
PMU_NODE_PE_CACHE
524+
} PMU_NODE_INFO_TYPE;
525+
526+
#define PMU_EVENT_INVALID 0xFFFFFFFF
527+
528+
typedef struct{
529+
uint32_t node_index;
530+
PMU_NODE_INFO_TYPE node_type;
531+
PMU_EVENT_TYPE_e event_desc;
532+
uint32_t event_id;
533+
} PLATFORM_OVERRIDE_EVENT_DETAILS;

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