enhancement(pcie): add test coverage for PCI_MM_02

- Add p106_entry and p107_entry in p045.c using existing payload flow
- Keep BAR discovery/access in payload; keep ioremap in helper
- Select mapping attribute per entry:
    - p045/p103 -> DEVICE_nGnRnE
    - p106/p107 -> NORMAL_NC
- Tag p106/p107 test entries with rule PCI_MM_02
- Add prototypes for p106_entry/p107_entry in acs_pcie.h
- Extend TEST_ENTRY_ID_e with PCI_MM_02_ENTRY, P106_ENTRY, P107_ENTRY
- Add pci_mm_02_entry wrapper and declaration
- Register P106/P107/PCI_MM_02 function pointers in rule_metadata.c tables

Signed-off-by: Sujana M <sujana.murali@arm.com>
Change-Id: Ia28b14bd12419ad2d60d678043385a321918f464

Author: Sujana-M

test_pool/pcie/p045.c

@@ -25,14 +25,19 @@ test_config_t test_entries[] = {
     /* p045 targets EP, RP, DP, and UP, and is executed for BSA */
     { ACS_PCIE_TEST_NUM_BASE + 45, "PCIe Device Memory mapping support    ", "PCI_MM_01"},
     /* p103 targets RCiEP, RCEC, iEP_EP, and iEP_RP, and is executed for SBSA */
-    { ACS_PCIE_TEST_NUM_BASE + 103, "PCIe Device Memory mapping support    ", "PCI_MM_01"}
+    { ACS_PCIE_TEST_NUM_BASE + 103, "PCIe Device Memory mapping support    ", "PCI_MM_01"},
+    /* p106 targets EP, RP, DP, and UP, and maps BAR to NORMAL memory */
+    { ACS_PCIE_TEST_NUM_BASE + 106, "PCIe Device Memory mapping support    ", "PCI_MM_02"},
+    /* p107 targets RCiEP, RCEC, iEP_EP, and iEP_RP, and maps BAR to NORMAL memory */
+    { ACS_PCIE_TEST_NUM_BASE + 107, "PCIe Device Memory mapping support    ", "PCI_MM_02"}
 };
 
 #define DATA 0xC0DECAFE
 
 static void *branch_to_test;
 static uint32_t test_num;
 static uint32_t onchip_peripherals_check;
+static uint32_t memory_map_attr;
 
 static
 void
@@ -47,9 +52,16 @@ esr(uint64_t interrupt_type, void *context)
   val_set_status(index, RESULT_FAIL(02));
 }
 
+static
+uint32_t
+map_device_memory(uint64_t base, char **baseptr)
+{
+  return val_memory_ioremap((void *)base, 1024, memory_map_attr, (void **)baseptr);
+}
+
 static
 void
-payload(void)
+payload_check_device_mem_map(void)
 {
   uint32_t data;
   uint32_t old_data;
@@ -102,10 +114,10 @@ payload(void)
       if (onchip_peripherals_check) {
           if ((dp_type != iEP_EP) && (dp_type != iEP_RP) && (dp_type != RCEC) && (dp_type != RCiEP))
               continue;
-          } else {
+      } else {
           if ((dp_type != EP) && (dp_type != RP) && (dp_type != DP) && (dp_type != UP))
               continue;
-          }
+      }
 
       val_print(DEBUG, "\n   BDF under check %08x", bdf);
       val_pcie_read_cfg(bdf, TYPE01_RIDR, &reg_value);
@@ -138,13 +150,13 @@ payload(void)
 
           if (bar_value == 0)
           {
-              /** This BAR is not implemented **/
+              /* This BAR is not implemented */
               val_print(DEBUG, "\n       BAR is not implemented for BDF 0x%x", bdf);
               goto next_bar;
           }
 
           /* Skip for IO address space */
-          if (bar_value & 0x1) {
+          if (bar_value & BAR_VALUE_IO_MASK) {
               val_print(DEBUG, "\n       BAR is used for IO address space request");
               val_print(DEBUG, " for BDF 0x%x", bdf);
               goto next_bar;
@@ -154,30 +166,29 @@ payload(void)
           {
               val_print(TRACE,
                         "\n       The BAR supports 64-bit address decoding capability");
-              val_pcie_read_cfg(bdf, offset+4, &bar_value_1);
+              val_pcie_read_cfg(bdf, offset + BAR_32B_OFFSET, &bar_value_1);
               base = bar_value_1;
 
               /* BAR supports 64-bit address therefore, write all 1's
                * to BARn and BARn+1 and identify the size requested
                */
               val_pcie_write_cfg(bdf, offset, 0xFFFFFFF0);
-              val_pcie_write_cfg(bdf, offset + 4, 0xFFFFFFFF);
+              val_pcie_write_cfg(bdf, offset + BAR_32B_OFFSET, 0xFFFFFFFF);
               val_pcie_read_cfg(bdf, offset, &bar_reg_lower_value);
               bar_size = bar_reg_lower_value & 0xFFFFFFF0;
-              val_pcie_read_cfg(bdf, offset + 4, &bar_reg_value);
+              val_pcie_read_cfg(bdf, offset + BAR_32B_OFFSET, &bar_reg_value);
               bar_upper_bits = bar_reg_value;
-              bar_size = bar_size | (bar_upper_bits << 32 );
+              bar_size = bar_size | (bar_upper_bits << 32);
               bar_size = ~bar_size + 1;
 
               /* Restore the original BAR value */
-              val_pcie_write_cfg(bdf, offset + 4, bar_value_1);
+              val_pcie_write_cfg(bdf, offset + BAR_32B_OFFSET, bar_value_1);
               val_pcie_write_cfg(bdf, offset, bar_value);
               base = (base << 32) | (bar_value & BAR_MASK);
           }
-
           else {
               val_print(TRACE,
-                         "\n       The BAR supports 32-bit address decoding capability");
+                        "\n       The BAR supports 32-bit address decoding capability");
 
               /* BAR supports 32-bit address. Write all 1's
                * to BARn and identify the size requested
@@ -210,11 +221,10 @@ payload(void)
 
           test_skip = 0;
 
-          /* Map the BARs to a DEVICE memory (non-cachable) attribute
+          /* Map the BARs to a memory attribute mentioned
            * and check transaction.
            */
-          status = val_memory_ioremap((void *)base, 1024, DEVICE_nGnRnE, (void **)&baseptr);
-
+          status = map_device_memory(base, &baseptr);
           /* Handle unimplemented PAL -> Report WARN */
           if (status == ACS_STATUS_PAL_NOT_IMPLEMENTED) {
             goto test_status;
@@ -229,7 +239,7 @@ payload(void)
 
           test_warn = 0;
 
-          /* Access check. Not performing data comparison check. */
+          /* Access check inside payload after obtaining BAR base and mapping */
           old_data = *(uint32_t *)(baseptr);
           *(uint32_t *)(baseptr) = DATA;
           data = *(uint32_t *)(baseptr);
@@ -248,10 +258,9 @@ payload(void)
 
 next_bar:
           if (BAR_REG(bar_value) == BAR_32_BIT)
-              offset = offset + 4;
-
-          if (BAR_REG(bar_value) == BAR_64_BIT)
-              offset = offset + 8;
+              offset = offset + BAR_32B_OFFSET;
+          else if (BAR_REG(bar_value) == BAR_64_BIT)
+              offset = offset + BAR_64B_OFFSET;
 
           if (msa_en)
               val_pcie_disable_msa(bdf);
@@ -273,11 +282,12 @@ payload(void)
       }
   } else if (test_warn) {
       val_set_status(index, RESULT_WARNING(1));
-  } else if (test_fail)
+  } else if (test_fail) {
       val_set_status(index, RESULT_FAIL(test_fail));
-  else
+  } else {
       val_set_status(index, RESULT_PASS);
   return;
+  }
 }
 
 uint32_t
@@ -287,13 +297,14 @@ p045_entry(uint32_t num_pe)
   uint32_t status = ACS_STATUS_FAIL;
   test_num = test_entries[0].test_num;
   onchip_peripherals_check = 0;
+  memory_map_attr = DEVICE_nGnRnE;
 
   num_pe = 1;  //This test is run on single processor
 
   val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__);
   status = val_initialize_test(test_num, test_entries[0].desc, num_pe);
   if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(test_num, num_pe, payload, 0);
+      val_run_test_payload(test_num, num_pe, payload_check_device_mem_map, 0);
 
   /* get the result from all PE and check for failure */
   status = val_check_for_error(test_num, num_pe, test_entries[0].rule);
@@ -310,13 +321,14 @@ p103_entry(uint32_t num_pe)
   uint32_t status = ACS_STATUS_FAIL;
   test_num = test_entries[1].test_num;
   onchip_peripherals_check = 1;
+  memory_map_attr = DEVICE_nGnRnE;
 
   num_pe = 1;  //This test is run on single processor
 
   val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__);
   status = val_initialize_test(test_num, test_entries[1].desc, num_pe);
   if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(test_num, num_pe, payload, 0);
+      val_run_test_payload(test_num, num_pe, payload_check_device_mem_map, 0);
 
   /* get the result from all PE and check for failure */
   status = val_check_for_error(test_num, num_pe, test_entries[1].rule);
@@ -325,3 +337,51 @@ p103_entry(uint32_t num_pe)
 
   return status;
 }
+
+uint32_t
+p106_entry(uint32_t num_pe)
+{
+
+  uint32_t status = ACS_STATUS_FAIL;
+  test_num = test_entries[2].test_num;
+  onchip_peripherals_check = 0;
+  memory_map_attr = NORMAL_NC;
+
+  num_pe = 1;  //This test is run on single processor
+
+  val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__);
+  status = val_initialize_test(test_num, test_entries[2].desc, num_pe);
+  if (status != ACS_STATUS_SKIP)
+      val_run_test_payload(test_num, num_pe, payload_check_device_mem_map, 0);
+
+  /* get the result from all PE and check for failure */
+  status = val_check_for_error(test_num, num_pe, test_entries[2].rule);
+
+  val_report_status(0, ACS_END(test_num), test_entries[2].rule);
+
+  return status;
+}
+
+uint32_t
+p107_entry(uint32_t num_pe)
+{
+
+  uint32_t status = ACS_STATUS_FAIL;
+  test_num = test_entries[3].test_num;
+  onchip_peripherals_check = 1;
+  memory_map_attr = NORMAL_NC;
+
+  num_pe = 1;  //This test is run on single processor
+
+  val_log_context((char8_t *)__FILE__, (char8_t *)__func__, __LINE__);
+  status = val_initialize_test(test_num, test_entries[3].desc, num_pe);
+  if (status != ACS_STATUS_SKIP)
+      val_run_test_payload(test_num, num_pe, payload_check_device_mem_map, 0);
+
+  /* get the result from all PE and check for failure */
+  status = val_check_for_error(test_num, num_pe, test_entries[3].rule);
+
+  val_report_status(0, ACS_END(test_num), test_entries[3].rule);
+
+  return status;
+}

val/include/acs_pcie.h

@@ -292,5 +292,7 @@ uint32_t p100_entry(uint32_t num_pe);
 uint32_t p103_entry(uint32_t num_pe); /* Linux test */
 uint32_t p104_entry(uint32_t num_pe); /* Linux test */
 uint32_t p105_entry(uint32_t num_pe); /* Linux test */
+uint32_t p106_entry(uint32_t num_pe); /* Linux test */
+uint32_t p107_entry(uint32_t num_pe); /* Linux test */
 
 #endif

val/include/acs_pcie_spec.h

@@ -130,6 +130,8 @@
 #define BAR_BASE_MASK   0xfffffff
 
 /*BAR offset */
+#define BAR_32B_OFFSET            4
+#define BAR_64B_OFFSET            8
 #define BAR0_OFFSET               0x10
 #define BAR_TYPE_0_MAX_OFFSET     0x24
 #define BAR_TYPE_1_MAX_OFFSET     0x14

val/include/rule_based_execution_enum.h

@@ -856,6 +856,7 @@ typedef enum {
     PCI_LI_02_ENTRY,
     PCI_LI_03_ENTRY,
     PCI_MM_01_ENTRY,
+    PCI_MM_02_ENTRY,
     PCI_MM_03_ENTRY,
     P049_ENTRY,
     P095_ENTRY,
@@ -937,6 +938,8 @@ typedef enum {
     P068_ENTRY,
     P071_ENTRY,
     P103_ENTRY,
+    P106_ENTRY,
+    P107_ENTRY,
     E006_ENTRY,
     E019_ENTRY,
     E020_ENTRY,

val/include/test_wrappers.h

@@ -41,6 +41,7 @@ uint32_t ie_reg_3_entry(uint32_t num_pe);
 uint32_t pci_in_19_entry(uint32_t num_pe);
 uint32_t pci_li_01_entry(uint32_t num_pe);
 uint32_t pci_mm_01_entry(uint32_t num_pe);
+uint32_t pci_mm_02_entry(uint32_t num_pe);
 uint32_t pci_mm_03_entry(uint32_t num_pe);
 uint32_t ri_smu_1_entry(uint32_t num_pe);
 uint32_t cxl_02_entry(uint32_t num_pe);

val/src/rule_metadata.c

@@ -1951,6 +1951,13 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
             .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI | PLATFORM_LINUX,
             .flag             = BASE_RULE,
         },
+        [PCI_MM_02] = {
+            .test_entry_id    = PCI_MM_02_ENTRY,
+            .module_id        = PCIE,
+            .rule_desc        = "PCIe Non-Cacheable Memory mapping support",
+            .platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI | PLATFORM_LINUX,
+            .flag             = BASE_RULE,
+        },
         [PCI_MM_03] = {
             .test_entry_id    = PCI_MM_03_ENTRY,
             .module_id        = PCIE,
@@ -3282,9 +3289,6 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
         [PCI_LI_04] = {
             .module_id        = PCIE,
         },
-        [PCI_MM_02] = {
-            .module_id        = PCIE,
-        },
         [PCI_MM_04] = {
             .module_id        = PCIE,
         },
@@ -3438,10 +3442,13 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
     [P001_ENTRY] = p001_entry,
     [P045_ENTRY] = p045_entry, // used in wrapper.
     [P103_ENTRY] = p103_entry, // used in wrapper.
+    [P106_ENTRY] = p106_entry, // used in wrapper.
     [P094_ENTRY] = p094_entry, // used in wrapper.
     [P104_ENTRY] = p104_entry, // used in wrapper.
+    [P107_ENTRY] = p107_entry, // used in wrapper.
     [PCI_LI_02_ENTRY] = pci_li_02_entry,
     [PCI_MM_01_ENTRY] = pci_mm_01_entry,
+    [PCI_MM_02_ENTRY] = pci_mm_02_entry,
     [PCI_MM_03_ENTRY] = pci_mm_03_entry,
     [PCI_MSI_2_ENTRY] = pci_msi_2_entry,
     [D004_ENTRY] = d004_entry,
@@ -3549,6 +3556,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
     [PCI_LI_02_ENTRY]  = pci_li_02_entry,
     [PCI_LI_03_ENTRY]  = pci_li_03_entry,
     [PCI_MM_01_ENTRY]  = pci_mm_01_entry,
+    [PCI_MM_02_ENTRY]  = pci_mm_02_entry,
     [PCI_MM_03_ENTRY]  = pci_mm_03_entry,
     [PCI_MSI_2_ENTRY]  = pci_msi_2_entry,
     [PCI_PP_04_ENTRY]  = pci_pp_04_entry,
@@ -3977,6 +3985,8 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
     [P094_ENTRY] = p094_entry, // used in wrapper.
     [P103_ENTRY] = p103_entry, // used in wrapper.
     [P104_ENTRY] = p104_entry, // used in wrapper.
+    [P106_ENTRY] = p106_entry, // used in wrapper.
+    [P107_ENTRY] = p107_entry, // used in wrapper.
     [P105_ENTRY] = p105_entry,
     [PCI_IC_11_ENTRY] = pci_ic_11_entry,
     [PCI_IN_04_ENTRY] = pci_in_04_entry,
@@ -3988,6 +3998,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
     [PCI_LI_02_ENTRY] = pci_li_02_entry,
     [PCI_LI_03_ENTRY] = pci_li_03_entry,
     [PCI_MM_01_ENTRY] = pci_mm_01_entry,
+    [PCI_MM_02_ENTRY] = pci_mm_02_entry,
     [PCI_MM_03_ENTRY] = pci_mm_03_entry,
     [PCI_MSI_2_ENTRY] = pci_msi_2_entry,
     [PCI_PP_04_ENTRY] = pci_pp_04_entry,
@@ -4238,6 +4249,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
     [PCI_LI_02_ENTRY]  = pci_li_02_entry,
     [PCI_LI_03_ENTRY]  = pci_li_03_entry,
     [PCI_MM_01_ENTRY]  = pci_mm_01_entry,
+    [PCI_MM_02_ENTRY]  = pci_mm_02_entry,
     [PCI_MM_03_ENTRY]  = pci_mm_03_entry,
     [PCI_MSI_2_ENTRY]  = pci_msi_2_entry,
     [PCI_PP_04_ENTRY]  = pci_pp_04_entry,
@@ -4361,6 +4373,8 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
     [P018_ENTRY] = p018_entry, // used in wrapper.
     [P094_ENTRY] = p094_entry, // used in wrapper.
     [P104_ENTRY] = p104_entry, // used in wrapper.
+    [P106_ENTRY] = p106_entry, // used in wrapper.
+    [P107_ENTRY] = p107_entry, // used in wrapper.
     [P009_ENTRY] = p009_entry,
     [P095_ENTRY] = p095_entry,
     [P020_ENTRY] = p020_entry, // used in wrapper.

val/src/test_wrappers.c

@@ -319,6 +319,20 @@ pci_mm_01_entry(uint32_t num_pe)
     return run_pcie_static_and_exerciser(p_list, e_list, num_pe);
 }
 
+/* PCI_MM_02 */
+uint32_t
+pci_mm_02_entry(uint32_t num_pe)
+{
+#ifdef BSA_LINUX_BUILD
+    TEST_ENTRY_ID_e tst_entry_list[] = {PCI_MM_01_ENTRY, P106_ENTRY, TEST_ENTRY_SENTINEL};
+#else
+    TEST_ENTRY_ID_e tst_entry_list[] = {PCI_MM_01_ENTRY, P106_ENTRY, P107_ENTRY,
+                                        TEST_ENTRY_SENTINEL};
+#endif
+
+    return run_test_entries(tst_entry_list, num_pe);
+}
+
 /* PCI_MM_03 */
 uint32_t
 pci_mm_03_entry(uint32_t num_pe)