JiffyDOS Instability depending on CPU on v4

[gordonfpanam]

On one of three boards I built, JiffyDOS could not reliably read from an SD2IEC device aside from very short BASIC programs.

After trying to use Diag264’s extended port tests and probing P0 through P7 on the CPU, it appears the voltage levels of a high signal on the input pins P7, P6 and P4 seemed lower on the third build compared to the other two. The original got up to 3.22VDC on a high signal but the third only got to 3.11VDC.

After checking and correcting pull-up resistor lines on RP1, it was better but still not stable. By comparison, the stock firmware loader seemed fine, as was the fast loader used by Psytronix games.

Since the stock TED machines treat CPU pins P7 through P4 as inputs at all times, I tried adding pull-up resistors to each. This proved unnecessary for P7 and P6 since RP1 takes care of that, but adding a 10k pull-up to P4 seemed to permanently fix JiffyDOS, at least for my SD2IEC device.

I don’t understand why, since P4 has nothing to do with the IEC port, but it’s an input alongside the others, and P4 didn’t have any kind of pull-up in the schematic. But JiffyDOS is very sensitive to timing issues, and maybe P4 floating caused some issues reading the port register on this third build. Voltages for the P input lines was different, so maybe this third 8501 was more sensitive.

[SukkoPera]

Let's start with the following:

• P0/1/2/3 are outputs
• P4 is an input that is only used for reading from the Datassette.
• P5 does not exist
• P6/7 are pulled up by RP1

So a couple of things are weird:

• I see no reason why JiffyDOS should use P4, and if it does not, I don't see how that could influence the reading of the other pins unless RP1 is not mounted or not mounted correctly, so please check that.
• I have never measured them, but any pulled-up input pin should measure very close to +5V. The fact that you see ~3V is already suspicious. I will make my own measurements and report back. But again, this could be caused by a bad RP1.
• P4 is not pulled up probably because it only makes sense when it is drive by something else (i.e.: the Datassette) and I would expect that to have a totem-pole output providing sharp edges.

Bottom line: I don't have an explanation for this, but I will take some measurements and then we'll discuss again.

[gordonfpanam]

I confirmed that the pins for P6 and P7 have 1k to +5V. I had to replace RP1 with a 'pack of resistors' since there was a busted pin on my RP1 part, but I measured afterward and each of those are pulled up properly. Signals looked much better on P6 and P7 afterward - very solid +5 on a high and practically 0 on a low. But P4 was still iffy until I added a 10k pullup on that.

It might be that the kernal and gi.joe loaders mask P4 out when reading the port register and they don't care, but maybe JiffyDOS makes some assumptions.

I can only test the cassette port with the Diag264 loopback board I made. Somewhere I have a 1530 (VIC-20) datasette but it's in very rough shape and I haven't even attempted to test or restore it.