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OBI: Fix missing intf definition. Adjust coding style. #157 
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‎docs/cpuif/obi.rst‎

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Open Bus Interface (OBI)
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========================
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Implements the register block using an `OBI <https://github.com/openhwgroup/obi>`_
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CPU interface.
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The OBI interface comes in two i/o port flavors:
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SystemVerilog Interface
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* Command line: ``--cpuif obi``
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* Interface Definition: :download:`obi_intf.sv <../../hdl-src/obi_intf.sv>`
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* Class: :class:`peakrdl_regblock.cpuif.obi.OBI_Cpuif`
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Flattened inputs/outputs
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Flattens the interface into discrete input and output ports.
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* Command line: ``--cpuif obi-flat``
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* Class: :class:`peakrdl_regblock.cpuif.obi.OBI_Cpuif_flattened`

‎docs/index.rst‎

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cpuif/apb
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cpuif/axi4lite
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cpuif/avalon
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cpuif/obi
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cpuif/passthrough
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cpuif/internal_protocol
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cpuif/customizing

‎hdl-src/obi_intf.sv‎

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interface obi_intf #(
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parameter DATA_WIDTH = 32,
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parameter ADDR_WIDTH = 32,
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parameter ID_WIDTH = 1
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);
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logic req;
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logic gnt;
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logic [ADDR_WIDTH-1:0] addr;
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logic we;
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logic [DATA_WIDTH/8-1:0] be;
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logic [DATA_WIDTH-1:0] wdata;
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logic [ID_WIDTH-1:0] aid;
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logic rvalid;
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logic rready;
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logic [DATA_WIDTH-1:0] rdata;
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logic err;
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logic [ID_WIDTH-1:0] rid;
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modport manager (
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output req,
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input gnt,
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output addr,
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output we,
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output be,
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output wdata,
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output aid,
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input rvalid,
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output rready,
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input rdata,
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input err,
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input rid
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);
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modport subordinate (
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input req,
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output gnt,
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input addr,
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input we,
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input be,
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input wdata,
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input aid,
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output rvalid,
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input rready,
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output rdata,
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output err,
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output rid
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);
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endinterface

‎src/peakrdl_regblock/cpuif/base.py‎

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@@ -37,8 +37,8 @@ def port_declaration(self) -> str:
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@property
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def parameters(self) -> List[str]:
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"""
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Optional list of additional parameters this CPU interface provides to
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the module's definition
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Optional list of additional parameter declarations this CPU interface
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provides to the module's definition
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"""
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return []
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‎src/peakrdl_regblock/cpuif/obi/__init__.py‎

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from typing import List
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from ..base import CpuifBase
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class OBI_Cpuif(CpuifBase):
@@ -32,25 +34,25 @@ def port_declaration(self) -> str:
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lines = [
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# OBI Request Channel (A)
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"input wire " + self.signal("req"),
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"output logic " + self.signal("gnt"),
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f"input wire [{self.addr_width-1}:0] " + self.signal("addr"),
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"input wire " + self.signal("we"),
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f"input wire [{self.data_width//8-1}:0] " + self.signal("be"),
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f"input wire [{self.data_width-1}:0] " + self.signal("wdata"),
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f"input wire [{self.id_width-1}:0] " + self.signal("aid"),
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"input wire [ID_WIDTH-1:0] " + self.signal("aid"),
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# OBI Response Channel (R)
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"output logic " + self.signal("gnt"),
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"output logic " + self.signal("rvalid"),
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"input wire " + self.signal("rready"),
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f"output logic [{self.data_width-1}:0] " + self.signal("rdata"),
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f"output logic [{self.id_width-1}:0] " + self.signal("rid"),
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"output logic " + self.signal("err"),
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"input wire " + self.signal("rready"),
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"output logic [ID_WIDTH-1:0] " + self.signal("rid"),
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]
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return ",\n".join(lines)
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def signal(self, name: str) -> str:
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return "obi_" + name
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@property
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def id_width(self) -> int:
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return 1 # Default ID width
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def parameters(self) -> List[str]:
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return ["parameter ID_WIDTH = 1"]

‎src/peakrdl_regblock/cpuif/obi/obi_tmpl.sv‎

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else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits({{cpuif.signal("wdata")}}), {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH);
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end
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`endif
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{% endif -%}
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// OBI Interface Implementation
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// This register block acts as an OBI subordinate
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localparam int unsigned DATA_WIDTH = {{ds.package_name}}::{{ds.module_name.upper()}}_DATA_WIDTH;
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localparam int unsigned BYTES = DATA_WIDTH/8;
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{% endif -%}
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// State & holding regs
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logic is_active; // A request is being served (not yet fully responded)
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logic gnt_q; // one-cycle grant for A-channel
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logic rsp_pending; // response ready but not yet accepted by manager
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logic [DATA_WIDTH-1:0] rsp_rdata_q;
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logic rsp_err_q;
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logic [$bits({{cpuif.signal("aid")}})-1:0] rid_q;
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logic is_active; // A request is being served (not yet fully responded)
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logic gnt_q; // one-cycle grant for A-channel
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logic rsp_pending; // response ready but not yet accepted by manager
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logic [{{cpuif.data_width-1}}:0] rsp_rdata_q;
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logic rsp_err_q;
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logic [$bits({{cpuif.signal("rid")}})-1:0] rid_q;
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// Latch AID on accept to echo back the response
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always_ff {{get_always_ff_event(cpuif.reset)}} begin
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if ({{get_resetsignal(cpuif.reset)}}) begin
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is_active <= 1'b0;
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gnt_q <= 1'b0;
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rsp_pending <= 1'b0;
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rsp_rdata_q <= '0;
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rsp_err_q <= 1'b0;
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rid_q <= '0;
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if ({{get_resetsignal(cpuif.reset)}}) begin
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is_active <= 1'b0;
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gnt_q <= 1'b0;
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rsp_pending <= 1'b0;
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rsp_rdata_q <= '0;
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rsp_err_q <= 1'b0;
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rid_q <= '0;
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cpuif_req <= '0;
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cpuif_req_is_wr <= '0;
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cpuif_addr <= '0;
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cpuif_wr_data <= '0;
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cpuif_wr_biten <= '0;
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end else begin
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// defaults
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cpuif_req <= 1'b0;
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gnt_q <= {{cpuif.signal("req")}} & ~is_active;
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cpuif_req <= '0;
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cpuif_req_is_wr <= '0;
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cpuif_addr <= '0;
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cpuif_wr_data <= '0;
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cpuif_wr_biten <= '0;
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end else begin
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// defaults
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cpuif_req <= 1'b0;
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gnt_q <= {{cpuif.signal("req")}} & ~is_active;
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46-
// Accept new request when idle
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if (~is_active) begin
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if ({{cpuif.signal("req")}}) begin
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is_active <= 1'b1;
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cpuif_req <= 1'b1;
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cpuif_req_is_wr <= {{cpuif.signal("we")}};
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cpuif_addr <= {{cpuif.signal("addr")}};
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cpuif_wr_data <= {{cpuif.signal("wdata")}};
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rid_q <= {{cpuif.signal("aid")}};
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for (int i = 0; i < BYTES; i++) begin
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cpuif_wr_biten[i*8 +: 8] <= {8{ {{cpuif.signal("be")}}[i] }};
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// Accept new request when idle
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if (~is_active) begin
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if ({{cpuif.signal("req")}}) begin
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is_active <= 1'b1;
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cpuif_req <= 1'b1;
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cpuif_req_is_wr <= {{cpuif.signal("we")}};
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cpuif_addr <= {{cpuif.signal("addr")}};
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cpuif_wr_data <= {{cpuif.signal("wdata")}};
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rid_q <= {{cpuif.signal("aid")}};
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for (int i = 0; i < {{cpuif.data_width_bytes}}; i++) begin
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cpuif_wr_biten[i*8 +: 8] <= {8{ {{cpuif.signal("be")}}[i] }};
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end
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end
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end
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end
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end
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61-
// Capture response
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if (is_active && (cpuif_rd_ack || cpuif_wr_ack)) begin
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rsp_pending <= 1'b1;
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rsp_rdata_q <= cpuif_rd_data;
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rsp_err_q <= cpuif_rd_err | cpuif_wr_err;
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// NOTE: Keep 'is_active' asserted until the external R handshake completes
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end
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// Capture response
57+
if (is_active && (cpuif_rd_ack || cpuif_wr_ack)) begin
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rsp_pending <= 1'b1;
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rsp_rdata_q <= cpuif_rd_data;
60+
rsp_err_q <= cpuif_rd_err | cpuif_wr_err;
61+
// NOTE: Keep 'is_active' asserted until the external R handshake completes
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end
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69-
// Complete external R-channel handshake only if manager ready
70-
if (rsp_pending && {{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) begin
71-
rsp_pending <= 1'b0;
72-
is_active <= 1'b0; // free to accept the next request
64+
// Complete external R-channel handshake only if manager ready
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if (rsp_pending && {{cpuif.signal("rvalid")}} && {{cpuif.signal("rready")}}) begin
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rsp_pending <= 1'b0;
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is_active <= 1'b0; // free to accept the next request
68+
end
7369
end
74-
end
7570
end
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7772
// R-channel outputs (held stable while rsp_pending=1)
7873
assign {{cpuif.signal("rvalid")}} = rsp_pending;
79-
assign {{cpuif.signal("rdata")}} = rsp_rdata_q;
80-
assign {{cpuif.signal("err")}} = rsp_err_q;
81-
assign {{cpuif.signal("rid")}} = rid_q;
74+
assign {{cpuif.signal("rdata")}} = rsp_rdata_q;
75+
assign {{cpuif.signal("err")}} = rsp_err_q;
76+
assign {{cpuif.signal("rid")}} = rid_q;
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8378
// A-channel grant (registered one-cycle pulse when we accept a request)
8479
assign {{cpuif.signal("gnt")}} = gnt_q;
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// If OBI config RReady is disabled, tie it high in the top-level/TB.
87-
// `ifndef SYNTHESIS
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// initial begin
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// if (0) $display("RReady supported; tie high if unused.");
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// end
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// `endif

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