Move port list generation out of Jinja template. #125, #153

Author: amykyta3

src/peakrdl_regblock/exporter.py

@@ -175,6 +175,9 @@ def export(self, node: Union[RootNode, AddrmapNode], output_dir:str, **kwargs: A
         context = {
             "cpuif": self.cpuif,
             "hwif": self.hwif,
+            "module_has_parameters": self.module_has_parameters,
+            "get_module_parameter_list": self.get_module_parameter_list,
+            "get_module_port_list": self.get_module_port_list,
             "write_buffering": self.write_buffering,
             "read_buffering": self.read_buffering,
             "get_resetsignal": self.dereferencer.get_resetsignal,
@@ -206,6 +209,47 @@ def export(self, node: Union[RootNode, AddrmapNode], output_dir:str, **kwargs: A
         if hwif_report_file:
             hwif_report_file.close()
 
+    def module_has_parameters(self) -> bool:
+        return bool(self.cpuif.parameters)
+
+    def get_module_parameter_list(self) -> str:
+        return ",\n".join(self.cpuif.parameters)
+
+    def get_module_port_list(self) -> str:
+        groups = []
+
+        # Main clock & reset
+        clkrst = [
+            "input wire clk",
+            f"input wire {self.dereferencer.default_resetsignal_name}"
+        ]
+        groups.append(",\n".join(clkrst))
+
+        # Signals that were declared outside of the hierarchy of the addrmap
+        # being exported
+        out_of_hier_signals = []
+        for signal in self.ds.out_of_hier_signals.values():
+            if signal.width == 1:
+                out_of_hier_signals.append(f"input wire {kwf(signal.inst_name)}")
+            else:
+                out_of_hier_signals.append(f"input wire [{signal.width - 1}:0] {kwf(signal.inst_name)}")
+        if out_of_hier_signals:
+            groups.append(",\n".join(out_of_hier_signals))
+
+        # Parity check error output
+        if self.ds.has_paritycheck:
+            groups.append("output logic parity_error")
+
+        # CPU interface ports
+        groups.append(self.cpuif.port_declaration)
+
+        if self.hwif.has_input_struct or self.hwif.has_output_struct:
+            groups.append(self.hwif.port_declaration)
+
+        return ",\n\n".join(groups)
+
+
+
 
 class DesignState:
     """

src/peakrdl_regblock/hwif/__init__.py

@@ -108,10 +108,6 @@ def port_declaration(self) -> str:
         Returns the declaration string for all I/O ports in the hwif group
         """
 
-        # Assume get_package_declaration() is always called prior to this
-        assert self.has_input_struct is not None
-        assert self.has_output_struct is not None
-
         lines = []
         if self.has_input_struct:
             type_name = f"{self.top_node.inst_name}__in_t"

src/peakrdl_regblock/module_tmpl.sv

@@ -2,29 +2,10 @@
 //  https://github.com/SystemRDL/PeakRDL-regblock
 
 module {{ds.module_name}}
-    {%- if cpuif.parameters %} #(
-        {{",\n        ".join(cpuif.parameters)}}
+    {%- if module_has_parameters() %} #(
+        {{get_module_parameter_list()|indent(8)}}
     ) {%- endif %} (
-        input wire clk,
-        input wire {{default_resetsignal_name}},
-
-        {%- for signal in ds.out_of_hier_signals.values() %}
-        {%- if signal.width == 1 %}
-        input wire {{kwf(signal.inst_name)}},
-        {%- else %}
-        input wire [{{signal.width-1}}:0] {{kwf(signal.inst_name)}},
-        {%- endif %}
-        {%- endfor %}
-
-        {%- if ds.has_paritycheck %}
-
-        output logic parity_error,
-        {%- endif %}
-
-        {{cpuif.port_declaration|indent(8)}}
-        {%- if hwif.has_input_struct or hwif.has_output_struct %},{% endif %}
-
-        {{hwif.port_declaration|indent(8)}}
+        {{get_module_port_list()|indent(8)}}
     );
 
     //--------------------------------------------------------------------------