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lines changed Original file line number Diff line number Diff line change @@ -9,4 +9,4 @@ Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
99For the command line tool, see the [ PeakRDL project] ( https://peakrdl.readthedocs.io ) .
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1111## Documentation
12- See the [ PeakRDL-regblock Documentation] ( http ://peakrdl-regblock.readthedocs.io) for more details
12+ See the [ PeakRDL-regblock Documentation] ( https ://peakrdl-regblock.readthedocs.io) for more details
Original file line number Diff line number Diff line change @@ -25,6 +25,13 @@ The easiest way to use PeakRDL-regblock is via the `PeakRDL command line tool <
2525 peakrdl regblock atxmega_spi.rdl -o regblock/ --cpuif axi4-lite
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28+ Looking for VHDL?
29+ -----------------
30+ This project generates SystemVerilog RTL. If you prefer using VHDL, check out
31+ the sister project which aims to be a feature-equivalent fork of
32+ PeakRDL-regblock: `PeakRDL-regblock-VHDL <https://peakrdl-regblock-vhdl.readthedocs.io >`_
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2835Links
2936-----
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