[BUG] Does not generate `hwenable` RTL for `intr` fields

[lizhiliTT]

Hello Alex,

I seem to have found another bug. I am using the RDL file below:

addrmap city {
    reg BUILDING_0 {
        field {
            sw = rw;
            hw = w;
            level intr;
            woclr;
        } ROOM[31:0] = 0x0;
    };

    reg BUILDING_1 {
        field {
            sw = rw;
            hw = w;
        } ROOM[31:0] = 0x0;
    };

    BUILDING_0 BUILDING_0 @ 0x0;
    BUILDING_1 BUILDING_1 @ 0x4;

    BUILDING_0.ROOM->hwenable = BUILDING_1.ROOM;
};

The tool stopped generating the RTL for the hwenable property as soon as I put in the level intr property:

• Before:

        if(decoded_reg_strb.BUILDING_0 && decoded_req_is_wr) begin // SW write
            next_c = (field_storage.BUILDING_0.ROOM.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
            load_next_c = '1;
        end else begin // HW Write
            next_c = hwif_in.BUILDING_0.ROOM.next & field_storage.BUILDING_1.ROOM.value | field_storage.BUILDING_0.ROOM.value & ~field_storage.BUILDING_1.ROOM.value;
            load_next_c = '1;
        end

• After:

        if(decoded_reg_strb.BUILDING_0 && decoded_req_is_wr) begin // SW write 1 clear
            next_c = field_storage.BUILDING_0.ROOM.value & ~(decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
            load_next_c = '1;
        end else if(hwif_in.BUILDING_0.ROOM.next != '0) begin // stickybit
            next_c = field_storage.BUILDING_0.ROOM.value | hwif_in.BUILDING_0.ROOM.next;
            load_next_c = '1;
        end

May you look into this? Thanks!

Regards,
Leo Li

[amykyta3]

Thanks for reporting, and agree this is a bug!

Confirming that the hwenable mechanism is not implemented for the field variants that define interrupts.