Describe the problem/limitation you think should be addressed
Currently the generated AXI-4 Lite regblock leaves all 8 AXI interface output signals (awready, bresp, etc) unregistered and driven by combinational logic. This is bad practice for timing and can result in timing issues for designs running at higher speeds. The existing pipelining options --rt-read-fanin and --rt-read-response are great but only affect internal datapaths.
Describe the solution you'd like
My request is to add a command line option to generate the regblock code with all output signals fully registered for tighter timing. This would increase latency of register access, but register access speed/throughput is typically not the bottleneck in designs.
Describe alternatives you've considered
One could place custom glue logic outside of the regblock module to register things. But adding the option internally to regblock is ideal.
Additional context
I haven't looked into the design enough to know if simply registering the existing output signals would work without screwing up AXI handshakes and/or internal logic, or if more involved design changes are needed
Thank you and great project!
Describe the problem/limitation you think should be addressed
Currently the generated AXI-4 Lite regblock leaves all 8 AXI interface output signals (
awready,bresp, etc) unregistered and driven by combinational logic. This is bad practice for timing and can result in timing issues for designs running at higher speeds. The existing pipelining options--rt-read-faninand--rt-read-responseare great but only affect internal datapaths.Describe the solution you'd like
My request is to add a command line option to generate the regblock code with all output signals fully registered for tighter timing. This would increase latency of register access, but register access speed/throughput is typically not the bottleneck in designs.
Describe alternatives you've considered
One could place custom glue logic outside of the regblock module to register things. But adding the option internally to regblock is ideal.
Additional context
I haven't looked into the design enough to know if simply registering the existing output signals would work without screwing up AXI handshakes and/or internal logic, or if more involved design changes are needed
Thank you and great project!