55
66from .definition_generator import DefinitionGenerator
77from .stringify import stringify_rdl_value
8+ from .identifier_filter import kw_filter as kwf
89
910if TYPE_CHECKING :
1011 from systemrdl .node import AddressableNode
@@ -14,9 +15,9 @@ class RDLGenerator(DefinitionGenerator, RDLListener):
1415 def get_content (self , node : 'Node' ) -> str :
1516
1617 if node .type_name is not None :
17- type_name = node .type_name
18+ type_name = kwf ( node .type_name )
1819 else :
19- type_name = node .inst_name
20+ type_name = kwf ( node .inst_name )
2021
2122 self .start ("addrmap" , type_name )
2223 self .assign_properties (node )
@@ -39,7 +40,7 @@ def assign_properties(self, node: 'Node') -> None:
3940 self .add_content (f"{ prop_name } = { value_s } ;" )
4041
4142 def define_enum (self , enum : Type [rdltypes .UserEnum ])-> None :
42- self .push (f"enum { enum .type_name } " , "" )
43+ self .push (f"enum { kwf ( enum .type_name ) } " , "" )
4344 for identifier , member in enum .members .items ():
4445 if member .rdl_name or member .rdl_desc :
4546 self .add_content (f"{ identifier } = { member .value } {{" )
@@ -61,22 +62,22 @@ def get_addressable_assignment(self, node: 'AddressableNode') -> str:
6162
6263 def enter_Addrmap (self , node : 'AddrmapNode' ) -> None :
6364 suffix = self .get_addressable_assignment (node )
64- self .push ("addrmap" , node .inst_name , node .array_dimensions , suffix )
65+ self .push ("addrmap" , kwf ( node .inst_name ) , node .array_dimensions , suffix )
6566 self .assign_properties (node )
6667
6768 def enter_Regfile (self , node : 'RegfileNode' ) -> None :
6869 suffix = self .get_addressable_assignment (node )
69- self .push ("regfile" , node .inst_name , node .array_dimensions , suffix , node .external )
70+ self .push ("regfile" , kwf ( node .inst_name ) , node .array_dimensions , suffix , node .external )
7071 self .assign_properties (node )
7172
7273 def enter_Mem (self , node : 'MemNode' ) -> None :
7374 suffix = self .get_addressable_assignment (node )
74- self .push ("mem" , node .inst_name , node .array_dimensions , suffix , True )
75+ self .push ("mem" , kwf ( node .inst_name ) , node .array_dimensions , suffix , True )
7576 self .assign_properties (node )
7677
7778 def enter_Reg (self , node : 'RegNode' ) -> None :
7879 suffix = self .get_addressable_assignment (node )
79- self .push ("reg" , node .inst_name , node .array_dimensions , suffix , node .external )
80+ self .push ("reg" , kwf ( node .inst_name ) , node .array_dimensions , suffix , node .external )
8081 self .assign_properties (node )
8182
8283 def enter_Field (self , node : 'FieldNode' ) -> None :
@@ -85,7 +86,7 @@ def enter_Field(self, node: 'FieldNode') -> None:
8586 if isinstance (reset , int ):
8687 suffix += f" = 0x{ reset :X} "
8788
88- self .push ("field" , node .inst_name , suffix = suffix , is_external = node .external )
89+ self .push ("field" , kwf ( node .inst_name ) , suffix = suffix , is_external = node .external )
8990
9091 encode = node .get_property ('encode' )
9192 if encode is not None :
@@ -94,7 +95,7 @@ def enter_Field(self, node: 'FieldNode') -> None:
9495 self .assign_properties (node )
9596
9697 def enter_Signal (self , node : 'SignalNode' ) -> None :
97- self .push ("signal" , node .inst_name )
98+ self .push ("signal" , kwf ( node .inst_name ) )
9899 self .assign_properties (node )
99100
100101 def exit_Component (self , node : 'Node' ) -> None :
0 commit comments