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Description
Problem:
When the systemRDL code has enum values, those are not propagated to the generated UVM code
Descrption:
Consider the below systemRDL code:
addrmap enumeration_example__default_slv_mmap {
addrmap {
reg {
desc = "Mode of operation register";
regwidth = 0x20;
field {
enum F_enum_t {
SLEEP = 0;
HALT = 1;
TRANSMIT = 2;
RECEIVE = 3;
TRANSCEIVE = 4;
} ;
desc = "MODE
[Enum 0x0 = SLEEP]
[Enum 0x1 = HALT]
[Enum 0x2 = TRANSMIT]
[Enum 0x3 = RECEIVE]
[Enum 0x4 = TRANSCEIVE]";
sw = rw;
encode = F_enum_t;
hw = r;
} F[3:0];
} MODE @ 0x4;
} enumeration_example @ 0x0;
};
The generated RAL is as below:
// Reg - enumeration_example__default_slv_mmap::enumeration_example::MODE
class enumeration_example__default_slv_mmap__enumeration_example__MODE extends uvm_reg;
rand uvm_reg_field F;
function new(string name = "enumeration_example__default_slv_mmap__enumeration_example__MODE");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction : new
virtual function void build();
this.F = new("F");
this.F.configure(this, 4, 0, "RW", 0, 'h0, 1, 1, 0);
endfunction : build
endclass : enumeration_example__default_slv_mmap__enumeration_example__MODE
The expected RAL:
// Reg - enumeration_example__default_slv_mmap::enumeration_example::MODE
class enumeration_example__default_slv_mmap__enumeration_example__MODE extends uvm_reg;
rand uvm_reg_field F;
// Enum typedef for field F
typedef enum int unsigned {
SLEEP = 0,
HALT = 1,
TRANSMIT = 2,
RECEIVE = 3,
TRANSCEIVE = 4
} F_enum_t;
function new(string name = "enumeration_example__default_slv_mmap__enumeration_example__MODE");
super.new(name, 32, UVM_NO_COVERAGE);
endfunction : new
virtual function void build();
this.F = new("F");
this.F.configure(this, 4, 0, "RW", 0, 'h0, 1, 1, 0);
endfunction : build
endclass : enumeration_example__default_slv_mmap__enumeration_example__MODE
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