[FEATURE] adding the register and fields name and description as comments in RTL and UVM

[imerkado91]

Hi!
Can we add a feature that will add the registers/fields names and descriptions from the RDL to the SystemVerilog files?

It will make debugging the modules much easier if the descriptions will also be embedded inside both regblock and UVM as comments, so we can easily understand which part is related to which register/field and what is its description and purpose (as given in the RDL)

Thanks!