[cpu] Fix some new clippy warnings (following rustup update).

youngman-g · youngman-g · commit 185c3d57d743 · 2025-07-04T21:52:51.000+01:00
diff --git a/cpu/src/alarm.rs b/cpu/src/alarm.rs
@@ -16,8 +16,8 @@ pub enum BadMemOp {
 impl Display for BadMemOp {
     fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), fmt::Error> {
         match self {
-            BadMemOp::Read(addr) => write!(f, "memory read from {:>013o} failed", addr),
-            BadMemOp::Write(addr) => write!(f, "memory write to {:>013o} failed", addr),
+            BadMemOp::Read(addr) => write!(f, "memory read from {addr:>013o} failed"),
+            BadMemOp::Write(addr) => write!(f, "memory write to {addr:>013o} failed"),
         }
     }
 }
@@ -252,15 +252,13 @@ impl Display for AlarmDetails {
             QSAL(instruction, op, msg) => {
                 write!(
                     f,
-                    "QSAL: during execution of instruction {:?}, {}: {}",
-                    instruction, op, msg,
+                    "QSAL: during execution of instruction {instruction:?}, {op}: {msg}",
                 )
             }
             PSAL(address, msg) => {
                 write!(
                     f,
-                    "PSAL: P register set to illegal address {:>06o}: {}",
-                    address, msg
+                    "PSAL: P register set to illegal address {address:>06o}: {msg}",
                 )
             }
             OCSAL(inst, msg) => {
@@ -274,8 +272,7 @@ impl Display for AlarmDetails {
             ROUNDTUITAL(msg) => {
                 write!(
                     f,
-                    "ROUNDTUITAL: the program used a feature not supported in the emulator: {}",
-                    msg
+                    "ROUNDTUITAL: the program used a feature not supported in the emulator: {msg}",
                 )
             }
 
@@ -284,11 +281,11 @@ impl Display for AlarmDetails {
                 operand,
                 message,
             } => {
-                write!(f, "IOSAL: I/O alarm during operation on unit {:o}", unit,)?;
+                write!(f, "IOSAL: I/O alarm during operation on unit {unit:o}")?;
                 if let Some(oper) = operand {
-                    write!(f, " with operand {}", oper)?;
+                    write!(f, " with operand {oper}")?;
                 }
-                write!(f, ": {}", message)
+                write!(f, ": {message}")
             }
 
             MISAL { affected_unit } => write!(
@@ -317,8 +314,7 @@ impl Display for AlarmDetails {
             DEFERLOOPAL { address } => {
                 write!(
                     f,
-                    "DEFERLOOPAL: infinite loop in deferred address at {:>012o}",
-                    address,
+                    "DEFERLOOPAL: infinite loop in deferred address at {address:>012o}",
                 )
             }
         }
@@ -338,7 +334,7 @@ impl Display for UnmaskedAlarm {
     fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), fmt::Error> {
         write!(f, "unmasked alarm {}", self.alarm)?;
         if let Some(address) = self.address {
-            write!(f, "at address {}", address)
+            write!(f, "at address {address}")
         } else {
             Ok(())
         }
diff --git a/cpu/src/control.rs b/cpu/src/control.rs
@@ -429,7 +429,7 @@ impl ResetMode {
                         Some(physical_address)
                     }
                     Err(e) => {
-                        panic!("failed to fetch reset {:?}: {}", self, e);
+                        panic!("failed to fetch reset {self:?}: {e}");
                     }
                 }
             }
@@ -1117,16 +1117,15 @@ impl ControlUnit {
                 _ => Err(Alarm {
                     sequence: control.regs.k,
                     details: AlarmDetails::ROUNDTUITAL(format!(
-                        "The emulator does not yet implement opcode {}",
-                        opcode,
+                        "The emulator does not yet implement opcode {opcode}",
                     )),
                 }),
             }
         }
 
         let seq_desc = match self.regs.k {
             None => "none".to_string(),
-            Some(n) => format!("{:02o}", n),
+            Some(n) => format!("{n:02o}"),
         };
 
         // Fetch the current instruction into the N register.
@@ -1288,19 +1287,15 @@ impl ControlUnit {
                     details: AlarmDetails::QSAL(
                         self.regs.n,
                         BadMemOp::Read(Unsigned36Bit::from(addr)),
-                        format!(
-                            "memory unit indicated address {:o} is not mapped",
-                            operand_address
-                        ),
+                        format!("memory unit indicated address {operand_address:o} is not mapped",),
                     ),
                 })?;
                 // QSAL is masked to we have to return some value, but
                 // we don't know what the TX-2 did in this case.
                 Err(self.alarm_unit.always_fire(Alarm {
                     sequence: self.regs.k,
                     details: AlarmDetails::ROUNDTUITAL(format!(
-                        "memory unit indicated address {:o} is not mapped and we don't know what to do when QSAL is masked",
-                        operand_address
+                        "memory unit indicated address {operand_address:o} is not mapped and we don't know what to do when QSAL is masked",
                     ))
                 }))
             }
@@ -1335,7 +1330,7 @@ impl ControlUnit {
                 details: AlarmDetails::QSAL(
                     self.regs.n,
                     BadMemOp::Write(Unsigned36Bit::from(*target)),
-                    format!("memory store to address {:#o} failed: {}", target, e,),
+                    format!("memory store to address {target:#o} failed: {e}",),
                 ),
             })?;
             Ok(()) // QSAL is masked, so just carry on.
diff --git a/cpu/src/control/op_configuration.rs b/cpu/src/control/op_configuration.rs
@@ -124,7 +124,7 @@ mod tests {
             .update_n_register(Instruction::from(&inst).bits())
             .expect(COMPLAIN);
         if let Err(e) = control.op_spg(ctx, &mut mem) {
-            panic!("SPG instruction failed: {}", e);
+            panic!("SPG instruction failed: {e}");
         }
 
         (
diff --git a/cpu/src/control/op_index.rs b/cpu/src/control/op_index.rs
@@ -411,7 +411,7 @@ mod tests {
                 .update_n_register(Instruction::from(&inst).bits())
                 .expect(COMPLAIN);
             if let Err(e) = control.op_aux(ctx, &mut mem) {
-                panic!("AUX instruction failed: {}", e);
+                panic!("AUX instruction failed: {e}");
             }
         }
         (control.regs.get_index_register(j), mem.get_e_register())
@@ -659,7 +659,7 @@ mod tests {
             .update_n_register(Instruction::from(&inst).bits())
             .expect(COMPLAIN);
         if let Err(e) = control.op_rsx(ctx, &mut mem) {
-            panic!("RSX instruction failed: {}", e);
+            panic!("RSX instruction failed: {e}");
         }
         (control.regs.get_index_register(j), mem.get_e_register())
     }
diff --git a/cpu/src/control/op_io.rs b/cpu/src/control/op_io.rs
@@ -114,8 +114,7 @@ impl ControlUnit {
                 Err(self.alarm_unit.always_fire(Alarm {
                     sequence: self.regs.k,
                     details: AlarmDetails::ROUNDTUITAL(format!(
-                        "IOS operand {:o}: Select Unit command is not yet implemented.",
-                        operand
+                        "IOS operand {operand:o}: Select Unit command is not yet implemented.",
                     )),
                 }))
             }
@@ -127,8 +126,7 @@ impl ControlUnit {
                         unit: j,
                         operand: Some(operand),
                         message: format!(
-                            "IOS operand {:o} has unrecognised leading command digit {:o}",
-                            operand, command,
+                            "IOS operand {operand:o} has unrecognised leading command digit {command:o}",
                         ),
                     },
                 })?;
diff --git a/cpu/src/control/op_jump.rs b/cpu/src/control/op_jump.rs
@@ -137,8 +137,7 @@ impl ControlUnit {
                         self.regs.n,
                         BadMemOp::Write(target.into()),
                         format!(
-                            "SKM instruction attempted to access address {:o} but it is not mapped",
-                            addr,
+                            "SKM instruction attempted to access address {addr:o} but it is not mapped",
                         ),
                     ),
                 })?;
@@ -153,9 +152,7 @@ impl ControlUnit {
                             self.regs.n,
                             BadMemOp::Write(target.into()),
                             format!(
-                                "SKM instruction attempted to modify (instruction configuration={:o}) a read-only location {:o}",
-                                cf,
-                                target,
+                                "SKM instruction attempted to modify (instruction configuration={cf:o}) a read-only location {target:o}",
                             ),
                         )
                     })?;
@@ -311,7 +308,7 @@ mod tests {
         let result = control.op_jmp(ctx, &mut mem);
         match result {
             Err(e) => {
-                panic!("JMP instruction failed: {}", e);
+                panic!("JMP instruction failed: {e}");
             }
             Ok(OpcodeResult {
                 program_counter_change: Some(ProgramCounterChange::Jump(to)),
@@ -857,14 +854,14 @@ mod tests {
             &UpdateE::No,
             &MetaBitChange::None,
         ) {
-            return Err(format!("failed to set up memory contents: {}", e));
+            return Err(format!("failed to set up memory contents: {e}"));
         }
         control
             .update_n_register(Instruction::from(inst).bits())
             .expect(COMPLAIN);
         let result = match control.op_sed(ctx, &mut mem) {
             Err(e) => {
-                return Err(format!("Execution of SED instruction failed: {}", e));
+                return Err(format!("Execution of SED instruction failed: {e}"));
             }
             Ok(result) => result,
         };
@@ -897,8 +894,7 @@ mod tests {
                 "SED instruction should not cause the current sequence's flag to drop".to_string(),
             ),
             Some(ProgramCounterChange::Stop(addr)) => Err(format!(
-                "SED instruction execution stopped at address {:?}",
-                addr
+                "SED instruction execution stopped at address {addr:?}",
             )),
         }
     }
@@ -917,7 +913,7 @@ mod tests {
                 panic!("{}", err);
             }
             Ok((Some(alarm), _)) => {
-                panic!("SED instruction unexpectedly raised an alarm {}", alarm);
+                panic!("SED instruction unexpectedly raised an alarm {alarm}");
             }
             Ok((None, skip)) => skip,
         }
diff --git a/cpu/src/control/op_loadstore.rs b/cpu/src/control/op_loadstore.rs
@@ -334,7 +334,7 @@ mod tests {
             ArithmeticUnitRegister::E => control.op_lde(ctx, &mut mem),
         };
         if let Err(e) = result {
-            panic!("{:?} instruction failed: {}", opcode, e);
+            panic!("{opcode:?} instruction failed: {e}");
         }
         (
             get_register_value(&mem, target_register),
@@ -386,7 +386,7 @@ mod tests {
         defer: bool,
         configuration: SystemConfiguration,
     ) -> (Unsigned36Bit, Unsigned36Bit) {
-        let complain = format!("failed to execute store instruction {:?}", opcode);
+        let complain = format!("failed to execute store instruction {opcode:?}");
         control.regs.f_memory[1] = configuration;
         let inst = SymbolicInstruction {
             held: false,
@@ -405,16 +405,16 @@ mod tests {
         let f = match opcode {
             Opcode::Ste => ControlUnit::op_ste,
             _ => {
-                panic!("opcode {:?} is not yet supported", opcode);
+                panic!("opcode {opcode:?} is not yet supported");
             }
         };
         if let Err(e) = f(control, ctx, mem) {
-            panic!("{:?} instruction failed: {}", opcode, e);
+            panic!("{opcode:?} instruction failed: {e}");
         }
         match mem.fetch(ctx, working_address, &MetaBitChange::None) {
             Ok((stored, _)) => (stored, mem.get_e_register()),
             Err(e) => {
-                panic!("unable to retrieve the stored word: {}", e);
+                panic!("unable to retrieve the stored word: {e}");
             }
         }
     }
diff --git a/cpu/src/exchanger.rs b/cpu/src/exchanger.rs
@@ -41,7 +41,7 @@ impl QuarterActivity {
     }
 
     pub(crate) fn is_active(&self, q: &u8) -> bool {
-        assert!(*q < 4, "invalid quarter {}", q);
+        assert!(*q < 4, "invalid quarter {q}");
         let mask = 1 << *q;
         self.0 & mask != 0
     }
diff --git a/cpu/src/io.rs b/cpu/src/io.rs
@@ -91,7 +91,7 @@ impl Display for TransferFailed {
             TransferFailed::BufferNotFree => {
                 f.write_str("Unit buffer not available for use by the CPU")
             }
-            TransferFailed::Alarm(alarm) => write!(f, "{}", alarm),
+            TransferFailed::Alarm(alarm) => write!(f, "{alarm}"),
         }
     }
 }
@@ -571,7 +571,7 @@ impl DeviceManager {
                     details: AlarmDetails::IOSAL {
                         unit,
                         operand: None,
-                        message: format!("unit {:o} is not known", unit),
+                        message: format!("unit {unit:o} is not known"),
                     },
                 })?;
                 // IOSAL is masked.
@@ -668,7 +668,7 @@ impl DeviceManager {
                                 details: AlarmDetails::IOSAL {
                                     unit: devno,
                                     operand: None,
-                                    message: format!("unit {} reports inability (EIA)", devno),
+                                    message: format!("unit {devno:o} reports inability (EIA)"),
                                 },
                             });
                         } else if unit_status.missed_data {
@@ -734,7 +734,7 @@ impl DeviceManager {
                     details: AlarmDetails::IOSAL {
                         unit: *device,
                         operand: None,
-                        message: format!("Attempt to disconnect missing unit {}", device),
+                        message: format!("Attempt to disconnect missing unit {device:o}"),
                     },
                 })?;
                 Ok(()) // IOSAL is masked, carry on.
@@ -763,7 +763,7 @@ impl DeviceManager {
                         details: AlarmDetails::IOSAL {
                             unit: *device,
                             operand: None,
-                            message: format!("Attempt to connect in-maint unit {}", device),
+                            message: format!("Attempt to connect in-maint unit {device:o}"),
                         },
                     })
                 } else {
@@ -783,7 +783,7 @@ impl DeviceManager {
                     details: AlarmDetails::IOSAL {
                         unit: *device,
                         operand: None,
-                        message: format!("Attempt to connect missing unit {}", device),
+                        message: format!("Attempt to connect missing unit {device:o}"),
                     },
                 })?;
                 Ok(None) // IOSAL is masked, carry on
diff --git a/cpu/src/memory.rs b/cpu/src/memory.rs
@@ -64,10 +64,10 @@ impl Display for MemoryOpFailure {
     fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), fmt::Error> {
         match self {
             MemoryOpFailure::NotMapped(addr) => {
-                write!(f, "address {:o} is not mapped to functioning memory", addr)
+                write!(f, "address {addr:o} is not mapped to functioning memory")
             }
             MemoryOpFailure::ReadOnly(addr, _extra) => {
-                write!(f, "address {:o}is mapped to read-only memory", addr)
+                write!(f, "address {addr:o}is mapped to read-only memory")
             }
         }
     }
@@ -1159,7 +1159,7 @@ fn test_write_all_mem() {
             }
             Err(MemoryOpFailure::NotMapped(_)) => (),
             Err(e) => {
-                panic!("Failure {:?} during write of memory address {:o}", e, addr);
+                panic!("Failure {e:?} during write of memory address {addr:o}");
             }
         }
     }
@@ -1184,7 +1184,7 @@ fn test_read_all_mem() {
             Ok(_) => (),
             Err(MemoryOpFailure::NotMapped(_)) => (),
             Err(e) => {
-                panic!("Failure {:?} during read of memory address {:o}", e, addr);
+                panic!("Failure {e:?} during read of memory address {addr:o}");
             }
         }
     }
diff --git a/cpu/src/tx2.rs b/cpu/src/tx2.rs
@@ -378,7 +378,7 @@ impl Tx2 {
             flag: self.control.current_flag_state(&seq),
             connected: false,
             in_maintenance: false,
-            name: format!("Sequence {:>02o}", seq),
+            name: format!("Sequence {seq:>02o}"),
             status: None,
             text_info: "(software only)".to_string(),
         }

Original file line number	Diff line number	Diff line change
`@@ -16,8 +16,8 @@ pub enum BadMemOp {`
`16`	`16`	`impl Display for BadMemOp {`
`17`	`17`	`fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), fmt::Error> {`
`18`	`18`	`match self {`
`19`		`- BadMemOp::Read(addr) => write!(f, "memory read from {:>013o} failed", addr),`
`20`		`- BadMemOp::Write(addr) => write!(f, "memory write to {:>013o} failed", addr),`
	`19`	`+ BadMemOp::Read(addr) => write!(f, "memory read from {addr:>013o} failed"),`
	`20`	`+ BadMemOp::Write(addr) => write!(f, "memory write to {addr:>013o} failed"),`
`21`	`21`	`}`
`22`	`22`	`}`
`23`	`23`	`}`
`@@ -252,15 +252,13 @@ impl Display for AlarmDetails {`
`252`	`252`	`QSAL(instruction, op, msg) => {`
`253`	`253`	`write!(`
`254`	`254`	`f,`
`255`		`- "QSAL: during execution of instruction {:?}, {}: {}",`
`256`		`- instruction, op, msg,`
	`255`	`+ "QSAL: during execution of instruction {instruction:?}, {op}: {msg}",`
`257`	`256`	`)`
`258`	`257`	`}`
`259`	`258`	`PSAL(address, msg) => {`
`260`	`259`	`write!(`
`261`	`260`	`f,`
`262`		`- "PSAL: P register set to illegal address {:>06o}: {}",`
`263`		`- address, msg`
	`261`	`+ "PSAL: P register set to illegal address {address:>06o}: {msg}",`
`264`	`262`	`)`
`265`	`263`	`}`
`266`	`264`	`OCSAL(inst, msg) => {`
`@@ -274,8 +272,7 @@ impl Display for AlarmDetails {`
`274`	`272`	`ROUNDTUITAL(msg) => {`
`275`	`273`	`write!(`
`276`	`274`	`f,`
`277`		`- "ROUNDTUITAL: the program used a feature not supported in the emulator: {}",`
`278`		`- msg`
	`275`	`+ "ROUNDTUITAL: the program used a feature not supported in the emulator: {msg}",`
`279`	`276`	`)`
`280`	`277`	`}`
`281`	`278`
`@@ -284,11 +281,11 @@ impl Display for AlarmDetails {`
`284`	`281`	`operand,`
`285`	`282`	`message,`
`286`	`283`	`} => {`
`287`		`- write!(f, "IOSAL: I/O alarm during operation on unit {:o}", unit,)?;`
	`284`	`+ write!(f, "IOSAL: I/O alarm during operation on unit {unit:o}")?;`
`288`	`285`	`if let Some(oper) = operand {`
`289`		`- write!(f, " with operand {}", oper)?;`
	`286`	`+ write!(f, " with operand {oper}")?;`
`290`	`287`	`}`
`291`		`- write!(f, ": {}", message)`
	`288`	`+ write!(f, ": {message}")`
`292`	`289`	`}`
`293`	`290`
`294`	`291`	`MISAL { affected_unit } => write!(`
`@@ -317,8 +314,7 @@ impl Display for AlarmDetails {`
`317`	`314`	`DEFERLOOPAL { address } => {`
`318`	`315`	`write!(`
`319`	`316`	`f,`
`320`		`- "DEFERLOOPAL: infinite loop in deferred address at {:>012o}",`
`321`		`- address,`
	`317`	`+ "DEFERLOOPAL: infinite loop in deferred address at {address:>012o}",`
`322`	`318`	`)`
`323`	`319`	`}`
`324`	`320`	`}`
`@@ -338,7 +334,7 @@ impl Display for UnmaskedAlarm {`
`338`	`334`	`fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), fmt::Error> {`
`339`	`335`	`write!(f, "unmasked alarm {}", self.alarm)?;`
`340`	`336`	`if let Some(address) = self.address {`
`341`		`- write!(f, "at address {}", address)`
	`337`	`+ write!(f, "at address {address}")`
`342`	`338`	`} else {`
`343`	`339`	`Ok(())`
`344`	`340`	`}`
Original file line number	Diff line number	Diff line change
`@@ -124,7 +124,7 @@ mod tests {`
`124`	`124`	`.update_n_register(Instruction::from(&inst).bits())`
`125`	`125`	`.expect(COMPLAIN);`
`126`	`126`	`if let Err(e) = control.op_spg(ctx, &mut mem) {`
`127`		`- panic!("SPG instruction failed: {}", e);`
	`127`	`+ panic!("SPG instruction failed: {e}");`
`128`	`128`	`}`
`129`	`129`
`130`	`130`	`(`
Original file line number	Diff line number	Diff line change
`@@ -411,7 +411,7 @@ mod tests {`
`411`	`411`	`.update_n_register(Instruction::from(&inst).bits())`
`412`	`412`	`.expect(COMPLAIN);`
`413`	`413`	`if let Err(e) = control.op_aux(ctx, &mut mem) {`
`414`		`- panic!("AUX instruction failed: {}", e);`
	`414`	`+ panic!("AUX instruction failed: {e}");`
`415`	`415`	`}`
`416`	`416`	`}`
`417`	`417`	`(control.regs.get_index_register(j), mem.get_e_register())`
`@@ -659,7 +659,7 @@ mod tests {`
`659`	`659`	`.update_n_register(Instruction::from(&inst).bits())`
`660`	`660`	`.expect(COMPLAIN);`
`661`	`661`	`if let Err(e) = control.op_rsx(ctx, &mut mem) {`
`662`		`- panic!("RSX instruction failed: {}", e);`
	`662`	`+ panic!("RSX instruction failed: {e}");`
`663`	`663`	`}`
`664`	`664`	`(control.regs.get_index_register(j), mem.get_e_register())`
`665`	`665`	`}`
Original file line number	Diff line number	Diff line change
`@@ -334,7 +334,7 @@ mod tests {`
`334`	`334`	`ArithmeticUnitRegister::E => control.op_lde(ctx, &mut mem),`
`335`	`335`	`};`
`336`	`336`	`if let Err(e) = result {`
`337`		`- panic!("{:?} instruction failed: {}", opcode, e);`
	`337`	`+ panic!("{opcode:?} instruction failed: {e}");`
`338`	`338`	`}`
`339`	`339`	`(`
`340`	`340`	`get_register_value(&mem, target_register),`
`@@ -386,7 +386,7 @@ mod tests {`
`386`	`386`	`defer: bool,`
`387`	`387`	`configuration: SystemConfiguration,`
`388`	`388`	`) -> (Unsigned36Bit, Unsigned36Bit) {`
`389`		`- let complain = format!("failed to execute store instruction {:?}", opcode);`
	`389`	`+ let complain = format!("failed to execute store instruction {opcode:?}");`
`390`	`390`	`control.regs.f_memory[1] = configuration;`
`391`	`391`	`let inst = SymbolicInstruction {`
`392`	`392`	`held: false,`
`@@ -405,16 +405,16 @@ mod tests {`
`405`	`405`	`let f = match opcode {`
`406`	`406`	`Opcode::Ste => ControlUnit::op_ste,`
`407`	`407`	`_ => {`
`408`		`- panic!("opcode {:?} is not yet supported", opcode);`
	`408`	`+ panic!("opcode {opcode:?} is not yet supported");`
`409`	`409`	`}`
`410`	`410`	`};`
`411`	`411`	`if let Err(e) = f(control, ctx, mem) {`
`412`		`- panic!("{:?} instruction failed: {}", opcode, e);`
	`412`	`+ panic!("{opcode:?} instruction failed: {e}");`
`413`	`413`	`}`
`414`	`414`	`match mem.fetch(ctx, working_address, &MetaBitChange::None) {`
`415`	`415`	`Ok((stored, _)) => (stored, mem.get_e_register()),`
`416`	`416`	`Err(e) => {`
`417`		`- panic!("unable to retrieve the stored word: {}", e);`
	`417`	`+ panic!("unable to retrieve the stored word: {e}");`
`418`	`418`	`}`
`419`	`419`	`}`
`420`	`420`	`}`
Original file line number	Diff line number	Diff line change
`@@ -41,7 +41,7 @@ impl QuarterActivity {`
`41`	`41`	`}`
`42`	`42`
`43`	`43`	`pub(crate) fn is_active(&self, q: &u8) -> bool {`
`44`		`- assert!(*q < 4, "invalid quarter {}", q);`
	`44`	`+ assert!(*q < 4, "invalid quarter {q}");`
`45`	`45`	`let mask = 1 << *q;`
`46`	`46`	`self.0 & mask != 0`
`47`	`47`	`}`
Original file line number	Diff line number	Diff line change
`@@ -64,10 +64,10 @@ impl Display for MemoryOpFailure {`
`64`	`64`	`fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), fmt::Error> {`
`65`	`65`	`match self {`
`66`	`66`	`MemoryOpFailure::NotMapped(addr) => {`
`67`		`- write!(f, "address {:o} is not mapped to functioning memory", addr)`
	`67`	`+ write!(f, "address {addr:o} is not mapped to functioning memory")`
`68`	`68`	`}`
`69`	`69`	`MemoryOpFailure::ReadOnly(addr, _extra) => {`
`70`		`- write!(f, "address {:o}is mapped to read-only memory", addr)`
	`70`	`+ write!(f, "address {addr:o}is mapped to read-only memory")`
`71`	`71`	`}`
`72`	`72`	`}`
`73`	`73`	`}`
`@@ -1159,7 +1159,7 @@ fn test_write_all_mem() {`
`1159`	`1159`	`}`
`1160`	`1160`	`Err(MemoryOpFailure::NotMapped(_)) => (),`
`1161`	`1161`	`Err(e) => {`
`1162`		`- panic!("Failure {:?} during write of memory address {:o}", e, addr);`
	`1162`	`+ panic!("Failure {e:?} during write of memory address {addr:o}");`
`1163`	`1163`	`}`
`1164`	`1164`	`}`
`1165`	`1165`	`}`
`@@ -1184,7 +1184,7 @@ fn test_read_all_mem() {`
`1184`	`1184`	`Ok(_) => (),`
`1185`	`1185`	`Err(MemoryOpFailure::NotMapped(_)) => (),`
`1186`	`1186`	`Err(e) => {`
`1187`		`- panic!("Failure {:?} during read of memory address {:o}", e, addr);`
	`1187`	`+ panic!("Failure {e:?} during read of memory address {addr:o}");`
`1188`	`1188`	`}`
`1189`	`1189`	`}`
`1190`	`1190`	`}`