Skip to content

Commit 3bb0a80

Browse files
committed
[cpu] Increase logging level of a couple of unusual events.
- Fetch of an instruction by an unspecified sequence (was DEBUG, now ERROR) - Fetch of an invalid instruction (was DEBUG, now INFO).
1 parent d4844c6 commit 3bb0a80

File tree

1 file changed

+5
-3
lines changed

1 file changed

+5
-3
lines changed

cpu/src/control.rs

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -674,7 +674,9 @@ impl ControlUnit {
674674
fn calaco(&mut self) {
675675
self.clear_alarms();
676676
// TODO: there is currently no simulator representation for
677-
// STOP/START, but CALACO is supposed to perform START.
677+
// STOP/START, but CALACO is supposed to perform START. This
678+
// might be relevant because PRESET is supposet to have no
679+
// effect unless the computer is in the stopped state.
678680
}
679681

680682
fn clear_alarms(&mut self) {
@@ -1006,7 +1008,7 @@ impl ControlUnit {
10061008
);
10071009
} else {
10081010
event!(
1009-
Level::DEBUG, // TODO: perhaps this should be INFO.
1011+
Level::ERROR,
10101012
"Unspecified sequence fetched instruction {:>012o} from physical address {:>012o}",
10111013
instruction_word,
10121014
p_physical_address
@@ -1418,7 +1420,7 @@ impl ControlUnit {
14181420
}
14191421
} else {
14201422
event!(
1421-
Level::DEBUG, // TODO: perhaps this should be INFO.
1423+
Level::INFO,
14221424
"fetched instruction {:?} is invalid",
14231425
&self.regs.n
14241426
);

0 commit comments

Comments
 (0)