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[ImportVerilog] Modify sampled value functions to use Comb operators (llvm#9656)
1 parent 15f3650 commit e02f23c

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2 files changed

+21
-38
lines changed

2 files changed

+21
-38
lines changed

lib/Conversion/ImportVerilog/AssertionExpr.cpp

Lines changed: 17 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -309,27 +309,26 @@ FailureOr<Value> Context::convertAssertionSystemCallArity1(
309309
auto past =
310310
ltl::PastOp::create(builder, loc, value, 1, Value{})
311311
.getResult();
312-
auto notCurrent =
313-
ltl::NotOp::create(builder, loc, current).getResult();
314-
auto pastAndNotCurrent =
315-
ltl::AndOp::create(builder, loc, {notCurrent, past})
316-
.getResult();
317-
return pastAndNotCurrent;
312+
auto fell = comb::ICmpOp::create(builder, loc,
313+
comb::ICmpPredicate::ugt,
314+
past, current, false)
315+
.getResult();
316+
return fell;
318317
})
319318
// Translate $rose to x[0] ∧ ¬x[-1]
320319
.Case("$rose",
321320
[&]() -> Value {
322321
auto past =
323322
ltl::PastOp::create(builder, loc, value, 1, Value{})
324323
.getResult();
325-
auto notPast = comb::createOrFoldNot(loc, past, builder);
326324
auto current = value;
327-
auto notPastAndCurrent =
328-
ltl::AndOp::create(builder, loc, {current, notPast})
329-
.getResult();
330-
return notPastAndCurrent;
325+
auto rose = comb::ICmpOp::create(builder, loc,
326+
comb::ICmpPredicate::ult,
327+
past, current, false)
328+
.getResult();
329+
return rose;
331330
})
332-
// Translate $changed to x[0] != x[-1]
331+
// Translate $changed to ( ¬x[0] x[-1] ) ⋁ ( x[0] ∧ ¬x[-1] )
333332
.Case("$changed",
334333
[&]() -> Value {
335334
auto past =
@@ -338,7 +337,8 @@ FailureOr<Value> Context::convertAssertionSystemCallArity1(
338337
auto current = value;
339338
auto changed = comb::ICmpOp::create(builder, loc,
340339
comb::ICmpPredicate::ne,
341-
past, current, false);
340+
past, current, false)
341+
.getResult();
342342
return changed;
343343
})
344344
// Translate $stable to ( x[0] ∧ x[-1] ) ⋁ ( ¬x[0] ∧ ¬x[-1] )
@@ -347,21 +347,11 @@ FailureOr<Value> Context::convertAssertionSystemCallArity1(
347347
auto past =
348348
ltl::PastOp::create(builder, loc, value, 1, Value{})
349349
.getResult();
350-
auto notPast =
351-
ltl::NotOp::create(builder, loc, past).getResult();
352350
auto current = value;
353-
auto notCurrent =
354-
ltl::NotOp::create(builder, loc, value).getResult();
355-
auto pastAndCurrent =
356-
ltl::AndOp::create(builder, loc, {current, past})
357-
.getResult();
358-
auto notPastAndNotCurrent =
359-
ltl::AndOp::create(builder, loc, {notCurrent, notPast})
360-
.getResult();
361-
auto stable =
362-
ltl::OrOp::create(builder, loc,
363-
{pastAndCurrent, notPastAndNotCurrent})
364-
.getResult();
351+
auto stable = comb::ICmpOp::create(builder, loc,
352+
comb::ICmpPredicate::eq,
353+
past, current, false)
354+
.getResult();
365355
return stable;
366356
})
367357
.Case("$past",

test/Conversion/ImportVerilog/builtins.sv

Lines changed: 4 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -387,9 +387,7 @@ module SampleValueBuiltins #() (
387387
// CHECK-NEXT: [[C2_INT:%.+]] = moore.logic_to_int [[C2]] : l1
388388
// CHECK-NEXT: [[CURRENT:%.+]] = moore.to_builtin_int [[C2_INT]] : i1
389389
// CHECK-NEXT: [[PAST:%.+]] = ltl.past [[CURRENT]], 1 : i1
390-
// CHECK-NEXT: [[TRUE:%.+]] = hw.constant true
391-
// CHECK-NEXT: [[NOTPAST:%.+]] = comb.xor [[PAST]], [[TRUE]] : i1
392-
// CHECK-NEXT: [[NOTPASTANDCURRENT:%.+]] = ltl.and [[CURRENT]], [[NOTPAST]] : i1, i1
390+
// CHECK-NEXT: [[ROSE:%.+]] = comb.icmp ult [[PAST]], [[CURRENT]] : i1
393391
rising_clk: assert property (@(posedge clk_i) clk_i |=> $rose(clk_i));
394392
// CHECK: moore.procedure always {
395393
// CHECK-NEXT: [[C:%.+]] = moore.read [[CLKWIRE]] : <l1>
@@ -399,8 +397,7 @@ module SampleValueBuiltins #() (
399397
// CHECK-NEXT: [[C2_INT:%.+]] = moore.logic_to_int [[C2]] : l1
400398
// CHECK-NEXT: [[CURRENT:%.+]] = moore.to_builtin_int [[C2_INT]] : i1
401399
// CHECK-NEXT: [[PAST:%.+]] = ltl.past [[CURRENT]], 1 : i1
402-
// CHECK-NEXT: [[NOTCURRENT:%.+]] = ltl.not [[CURRENT]] : i1
403-
// CHECK-NEXT: [[PASTANDNOTCURRENT:%.+]] = ltl.and [[NOTCURRENT]], [[PAST]] : !ltl.property, i1
400+
// CHECK-NEXT: [[FELL:%.+]] = comb.icmp ugt [[PAST]], [[CURRENT]] : i1
404401
falling_clk: assert property (@(posedge clk_i) clk_i |=> $fell(clk_i));
405402
// CHECK: moore.procedure always {
406403
// CHECK-NEXT: [[C:%.+]] = moore.read [[CLKWIRE]] : <l1>
@@ -410,11 +407,7 @@ module SampleValueBuiltins #() (
410407
// CHECK-NEXT: [[C2_INT:%.+]] = moore.logic_to_int [[C2]] : l1
411408
// CHECK-NEXT: [[CURRENT:%.+]] = moore.to_builtin_int [[C2_INT]] : i1
412409
// CHECK-NEXT: [[PAST:%.+]] = ltl.past [[CURRENT]], 1 : i1
413-
// CHECK-NEXT: [[NOTPAST:%.+]] = ltl.not [[PAST]] : i1
414-
// CHECK-NEXT: [[NOTCURRENT:%.+]] = ltl.not [[CURRENT]] : i1
415-
// CHECK-NEXT: [[PASTANDCURRENT:%.+]] = ltl.and [[CURRENT]], [[PAST]] : i1, i1
416-
// CHECK-NEXT: [[NOTPASTANDNOTCURRENT:%.+]] = ltl.and [[NOTCURRENT]], [[NOTPAST]] : !ltl.property, !ltl.property
417-
// CHECK-NEXT: [[STABLE:%.+]] = ltl.or [[PASTANDCURRENT]], [[NOTPASTANDNOTCURRENT]] : i1, !ltl.property
410+
// CHECK-NEXT: [[STABLE:%.+]] = comb.icmp eq [[PAST]], [[CURRENT]] : i1
418411
stable_clk: assert property (@(posedge clk_i) clk_i |=> $stable(clk_i));
419412
// CHECK: moore.procedure always {
420413
// CHECK-NEXT: [[C:%.+]] = moore.read [[CLKWIRE]] : <l1>
@@ -424,7 +417,7 @@ module SampleValueBuiltins #() (
424417
// CHECK-NEXT: [[C2_INT:%.+]] = moore.logic_to_int [[C2]] : l1
425418
// CHECK-NEXT: [[CURRENT:%.+]] = moore.to_builtin_int [[C2_INT]] : i1
426419
// CHECK-NEXT: [[PAST:%.+]] = ltl.past [[CURRENT]], 1 : i1
427-
// CHECK-NEXT: [[STABLE:%.+]] = comb.icmp ne [[PAST]], [[CURRENT]] : i1
420+
// CHECK-NEXT: [[CHANGED:%.+]] = comb.icmp ne [[PAST]], [[CURRENT]] : i1
428421
changed_clk: assert property (@(posedge clk_i) clk_i |=> $changed(clk_i));
429422
// CHECK: moore.procedure always {
430423
// CHECK-NEXT: [[C:%.+]] = moore.read [[CLKWIRE]] : <l1>

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