arch: arm64: Convert cpu_idle from ASM to C

ASM is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.

There's a bug in current arch_cpu_atomic_idle asm version:
	tst	x0, #(DAIF_IRQ_BIT) //here Z := (DAIF_IRQ_BIT == 0)
	beq	_irq_disabled //jump to _irq_disabled when Z is set
	msr	daifclr, #(DAIFCLR_IRQ_BIT)
_irq_disabled:
	ret

As can be seen, the asm code jumps to _irq_disabled when Z is set, but
per aarch64 architecture reference, DAIF_IRQ == 0 means the IRQ is
unmasked, I.E enabled. So the asm logic here is wrong. I fixed this bug
in C version. This shows the benefit of ASM -> C

As for performance concern, except the bug fix above, there's no
difference of generated code between ASM and C version.
ASM version:
<arch_cpu_idle>:
d5033f9f 	dsb	sy
d503207f 	wfi
d50342ff 	msr	daifclr, #0x2
d65f03c0 	ret

arch_cpu_atomic_idle>:
d50342df 	msr	daifset, #0x2
d5033fdf 	isb
d503205f 	wfe
f279001f 	tst	x0, #0x80
54000040 	b.eq	1001d10 <_irq_disabled>  // b.none
d50342ff 	msr	daifclr, #0x2

_irq_disabled>:
d65f03c0 	ret

C version:
<arch_cpu_idle>:
d5033f9f 	dsb	sy
d503207f 	wfi
d50342ff 	msr	daifclr, #0x2
d65f03c0 	ret

<arch_cpu_atomic_idle>:
d50342df 	msr	daifset, #0x2
d5033fdf 	isb
d503205f 	wfe
37380040 	tbnz	w0, #7, 1001d0c <arch_cpu_atomic_idle+0x14>
d50342ff 	msr	daifclr, #0x2
d65f03c0 	ret

And as can be seen, C version use the tbnz instruction to test bit and
branch. Unlike TST, TBNZ does not affect the Z, N, C, or V flags in the
processor state. So except the bug fix, C version looks a bit better
than asm version.

Other architectures such as x86, riscv, rx, xtensa, mips and even arm
cortex_m also use c version for cpu_idle, it's safe for ASM -> C.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>

Author: xhackerustc

arch/arm64/core/CMakeLists.txt

@@ -3,7 +3,7 @@
 zephyr_library()
 
 zephyr_library_sources(
-  cpu_idle.S
+  cpu_idle.c
   early_mem_funcs.S
   fatal.c
   irq_init.c

arch/arm64/core/cpu_idle.S

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ * Copyright (c) 2026 Synaptics Incorporated
+ * Author: Jisheng Zhang <jszhang@kernel.org>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * ARM64 Cortex-A power management
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/tracing/tracing.h>
+
+#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE
+void arch_cpu_idle(void)
+{
+#if defined(CONFIG_TRACING)
+	sys_trace_idle();
+#endif
+
+	__asm__ volatile("dsb sy" : : : "memory");
+	wfi();
+
+#if defined(CONFIG_TRACING)
+	sys_trace_idle_exit();
+#endif
+
+	enable_irq();
+}
+#endif
+
+#ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
+void arch_cpu_atomic_idle(unsigned int key)
+{
+#if defined(CONFIG_TRACING)
+	sys_trace_idle();
+#endif
+
+	disable_irq();
+
+	__asm__ volatile("isb" : : : "memory");
+	wfe();
+
+#if defined(CONFIG_TRACING)
+	sys_trace_idle_exit();
+#endif
+
+	if (!(key & DAIF_IRQ_BIT)) {
+		enable_irq();
+	}
+}
+#endif