simplify implementation and remove pvt dependency

Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>

Author: dsengupta0628

docs/contrib/3DIC.md

@@ -307,22 +307,27 @@ create_clock -name clk -period 1.0 [get_pins -of_objects [get_nets clk_top]]
 now produces a constrained `Path Group: clk` setup check identical to
 the inner-CK form. Two fixes were required on top of Stage 7:
 
-**Fix A — Synthesize a LibertyCell per chip-master with a self-arc per
-chip-bump port.** `dbNetwork::makeTopCellForChip` builds the chip-master
-Cell *as* a `LibertyCell` (via `LibertyBuilder`) on a private
-`LibertyLibrary`. For each chip-bump bterm it creates a `LibertyPort`
-and a combinational self-arc (`lc->makeTimingArcSet(lp, lp, ...)`).
-`Graph::makeInstanceEdges` consumes the arc and creates:
-
-- `bump_load → bump_bidir_drvr` (forward combinational, traversable by
-  `SearchAdj`)
-- `bump_bidir_drvr → bump_load` (flagged `isBidirectInstPath`, filtered
-  by default predicate but harmless)
-
-The forward arc closes the gap between the load and driver vertices of
-the BIDIRECT chip-bump pin, so a clock arrival seeded on the load (or
-the driver) fans out via the regular wire-edge model. Zero arc delay
-preserves the inner-CK anchor's reported slack.
+**Fix A — Chip-bump pins report BIDIRECT; no synthesized timing arc.**
+`dbNetwork::makeTopCellForChip` builds one synthetic **`ConcreteCell`**
+per chip master (via the public `makeCell`/`makePort`), with a `Port`
+per chip-bump bterm. It has no `LibertyCell` binding, so
+`libertyPort(chip_bump_pin)` is null and `dbNetwork::direction(pin)`
+falls through to its `PortDirection::bidirect()` branch.
+
+Because the pin is BIDIRECT, `Graph::makePinVertices` allocates **two**
+vertices for it — a load and a driver — and `create_clock` seeds the
+clock arrival on **both** (`Search::findClockVertices` /
+`seedClkArrivals` insert both). The driver vertex then fans out into the
+chiplet body through the fat-net wire-edge model (see Stage 7), so the
+clock reaches each chiplet's internal CK. **No instance/timing arc is
+synthesized** — the load and driver vertices do not need to be joined by
+an edge, since both are seeded directly.
+
+(Historical note: an earlier revision synthesized a `LibertyCell` with a
+zero-delay combinational self-arc per bump via OpenSTA's private
+`LibertyBuilder`. That was dropped — the private header is not part of
+OpenSTA's public include API, and the arc turned out to be unnecessary
+for propagation. See the wire-load section for its QoR side effect.)
 
 **Fix B — Per-block discriminator in `getDbNwkObjectId`.** Each chiplet
 `dbBlock` numbers its iterms/bterms/insts/nets from 1. Without
@@ -353,11 +358,22 @@ STA does **not** build a per-segment drvr → load chain. `Graph::makeWireEdgesF
 
 1. **Cross-chiplet data edge has no intermediate bump-pin hop.** The wire edge `chipA/buf/Z → chipB/buf/A` is created in one shot when `chipA/q_bump` (the BIDIRECT driver iterated from chipA's chip_inst pin walk) is processed. The visitor descends into chipA's inner q dbNet (yielding `chipA/buf/Z`, `chipA.q_bterm`) and chipB's inner d dbNet (yielding `chipB/buf/A`, `chipB.d_bterm`). `FindNetDrvrLoads` then classifies — `chipA/buf/Z` joins `drvrs`, `chipB/buf/A` joins `loads` — and the pairwise loop emits the cross-chip wire edge.
 
-2. **Every BIDIRECT chip-bump appears in BOTH drvrs and loads.** `isDriver` and `isLoad` both return true for `direction == bidirect`. So `chipA/q_bump` and `chipB/d_bump` show up as loads in the aggregated set too, and `chipA/buf/Z` gets extra outgoing wire edges to their **load-side vertices** in addition to the real load `chipB/buf/A`. These edges are harmless for path search — the bump load vertex's only outgoing arc is the synthesized `load → bidir_drvr` self-arc, which then re-enters the same chipnet, and `SearchPred` (forward search) only emits paths via the `bidir_drvr_vertex`. No spurious paths form.
+2. **Every BIDIRECT chip-bump appears in BOTH drvrs and loads.** `isDriver` and `isLoad` both return true for `direction == bidirect`. So `chipA/q_bump` and `chipB/d_bump` show up as loads in the aggregated set too, and `chipA/buf/Z` gets extra outgoing wire edges to their **load-side vertices** in addition to the real load `chipB/buf/A`. These edges are harmless for path search — a bump load vertex has no outgoing arc (it is a dead-end load), and `SearchPred` (forward search) only emits paths via the `bidir_drvr_vertex`. No spurious paths form.
 
-3. **Wire-delay calc sees fanout count.** STA's default wire-load lookup uses fanout count (or summed pin caps; chip-bump LibertyPort cap defaults to 0). Every distinct load on a fat net contributes to the count. If two loads dedup on identity (`PinSet`/`NetSet` sort by `id()` — see the per-block discriminator section above), the fanout under-counts and wire delay drops by one tier.
+3. **Wire-delay calc sees fanout count.** STA's default wire-load lookup uses fanout count (or summed pin caps; chip-bump port cap defaults to 0). Every distinct load on a fat net contributes to the count. If two loads dedup on identity (`PinSet`/`NetSet` sort by `id()` — see the per-block discriminator section above), the fanout under-counts and wire delay drops by one tier.
 
-The Stage 7 golden `slack 0.83` was produced under exactly that under-count: cross-block iterm/bterm/net id collisions in `visited_drvrs` / `visited_nets` silently dropped some chip-side loads. After the `block_disc_` fix the load set is correctly sized, fanout grows, and the wire edge `chipA/buf/Z → chipB/buf/A` picks up an extra +0.01 ns, landing at `slack 0.82`. The regen captures the physical-topology-correct value.
+The `block_disc_` fix is what keeps the three cross-block loads on the
+`chipA/buf/Z` fat net distinct — `chipB/buf/A` (the far CMOS input) plus
+the two physical microbumps `chipA/q_bump` and `chipB/d_bump`. Fanout = 3,
+giving the constrained `slack 0.83`. Verify with
+`report_checks -fields {fanout}`: the `chipA/buf/Z` row shows `Fanout 3`.
+
+An earlier revision reported `slack 0.82` (fanout 4). That extra load was
+an artifact of the now-removed synthesized self-arc (Fix A history): its
+`load → bidir_drvr` edge let a bump's load vertex **re-enter** the chipnet
+during `visitConnectedPins`, so the same bond was counted twice. A bond is
+a single physical load, so `0.83` / fanout 3 is the physically-correct
+value; `0.82` was a one-tier over-count.
 
 ## term(Pin*) history (Stage 4–6.5)
 

docs/contrib/3DIC_TODO.md

@@ -210,13 +210,14 @@ TSV, microbump) contribute non-trivial RC.
 
 ### Problem
 
-v1 always synthesizes a stub `LibertyCell` per chiplet master with a
-zero-delay self-arc per chip-bump port. That works when the chiplet
-ships only as DEF + bump map. When the chiplet vendor instead ships an
-**Extracted Timing Model (ETM)** — a real `.lib` whose `cell` matches
-the chiplet name and whose ports match the chip-bump bterm names —
-the stub is wrong: it hides the ETM's real clock-to-q, setup/hold,
-and internal arcs.
+v1 builds a stub **`ConcreteCell`** (no `LibertyCell` binding) per
+chiplet master, with a plain `Port` per chip-bump bterm and no timing
+arc — cross-chiplet delay is cell logic plus (zero) bond wire delay only.
+That works when the chiplet ships only as DEF + bump map. When the
+chiplet vendor instead ships an **Extracted Timing Model (ETM)** — a real
+`.lib` whose `cell` matches the chiplet name and whose ports match the
+chip-bump bterm names — the stub is wrong: it hides the ETM's real
+clock-to-q, setup/hold, and internal arcs.
 
 3DBlox already supports this via `external.liberty_file:` under
 `ChipletDef:`. dbSta just doesn't consult it.
@@ -229,9 +230,9 @@ and internal arcs.
      LibertyCell* etm = network_->findLibertyCell(master->getName());
      if (etm) {
        chip_master_cells_[master] = reinterpret_cast<Cell*>(etm);
-       continue;  // skip stub synthesis
+       continue;  // skip stub ConcreteCell synthesis
      }
-     // no ETM — fall through to LibertyBuilder stub.
+     // no ETM — fall through to the public makeCell/makePort stub.
      ```
    - The ETM `LibertyCell`'s `LibertyPort`s must match the chip-bump
      bterm names. Validate via a sanity pass:
@@ -241,15 +242,15 @@ and internal arcs.
      }
      ```
 
-2. **Suppress the BIDIRECT direction override when ETM is present.**
-   - `dbNetwork::direction(chip_bump_pin)` currently returns BIDIRECT
-     unconditionally so wire-edge formation runs on every bump. With an
-     ETM, port direction should come from the ETM's `LibertyPort`
-     (which encodes the real INPUT/OUTPUT/INOUT semantics). The ETM
-     model itself drives clock-edge propagation through real arcs, no
-     BIDIRECT trick needed.
+2. **Suppress the BIDIRECT direction fallback when ETM is present.**
+   - For a stub `ConcreteCell` chip-bump pin, `libertyPort(pin)` is null,
+     so `dbNetwork::direction(pin)` returns BIDIRECT (dual vertices, both
+     clock-seeded — how v1 propagates a clock through a bump). With an
+     ETM the bump pin resolves to a real `LibertyPort`, so `direction`
+     returns its INPUT/OUTPUT/INOUT and the ETM's own arcs drive
+     clock-edge propagation; no BIDIRECT fallback is taken.
 
-3. **Skip the `chip_bump_lib_` private LibertyLibrary entirely** when
+3. **Skip the `chip_master_lib_` stub Library entirely** when
    every chiplet master has an ETM.
 
 4. **Diagnostic.**

src/dbSta/include/db_sta/dbNetwork.hh

@@ -516,11 +516,12 @@ class dbNetwork : public ConcreteNetwork
   // so iterms/bterms/insts/nets from different chiplet blocks (each
   // numbered from 1) don't collide in NetSet/PinSet keys.
   odb::PtrMap<odb::dbBlock, uint32_t> block_disc_;
-  // Synthetic LibertyLibrary for chip-master Cells. Each carries a
-  // self-arc per chip-bump port so Graph::makeInstanceEdges builds the
-  // internal load<->bidir_drvr edges that let create_clock anchors on
-  // chip-bump pins propagate into the chiplet body.
-  LibertyLibrary* chip_bump_lib_ = nullptr;
+  // Synthetic (non-Liberty) Library owning the chip-master Cells built in
+  // makeTopCellForChip. The Cells have no LibertyCell binding; a clock
+  // anchored on a chip-bump pin propagates because the pin is BIDIRECT
+  // (dual load/driver vertices, both clock-seeded) and the driver fans out
+  // via the fat-net wire-edge model — no synthesized timing arc.
+  Library* chip_master_lib_ = nullptr;
   Instance* top_instance_;
   Cell* top_cell_ = nullptr;
   std::set<dbNetworkObserver*> observers_;

src/dbSta/src/dbNetwork.cc

@@ -61,7 +61,6 @@ Recommended conclusion: use map for concrete cells. They are invariant.
 #include <vector>
 
 #include "dbEditHierarchy.hh"
-#include "liberty/LibertyBuilder.hh"
 #include "odb/PtrSetMap.h"
 #include "odb/db.h"
 #include "odb/dbObject.h"
@@ -80,8 +79,6 @@ Recommended conclusion: use map for concrete cells. They are invariant.
 #include "sta/PortDirection.hh"
 #include "sta/Search.hh"
 #include "sta/StringUtil.hh"
-#include "sta/TimingArc.hh"
-#include "sta/TimingRole.hh"
 #include "sta/VertexId.hh"
 #include "utl/Logger.h"
 #include "utl/algorithms.h"
@@ -1008,45 +1005,39 @@ void dbNetwork::makeTopCellForChip(dbChip* chip)
     Library* old_lib = library(top_cell_);
     deleteLibrary(old_lib);
   }
-  if (chip_bump_lib_) {
-    deleteLibrary(reinterpret_cast<Library*>(chip_bump_lib_));
-    chip_bump_lib_ = nullptr;
+  if (chip_master_lib_) {
+    deleteLibrary(chip_master_lib_);
+    chip_master_lib_ = nullptr;
   }
   chip_master_cells_.clear();
   const char* design_name = chip->getName();
   Library* top_lib = makeLibrary(design_name, "");
   top_cell_ = makeCell(top_lib, design_name, false, "");
-  // Per-master LibertyCell with a self-arc per chip-bump port. Without
-  // the self-arc Graph::makeInstanceEdges builds no load<->bidir_drvr
-  // edge for the BIDIRECT bump pin, blocking create_clock propagation
-  // through the chip-bump.
-  chip_bump_lib_ = makeLibertyLibrary("3dic_chip_bump_lib", "");
-  LibertyBuilder builder(debug_, report_);
+  // One plain Cell per chip master with a Port per chip-bump bterm,
+  // backing cell()/port()/name()/direction() for chip-inst and chip-bump
+  // pins. No LibertyCell, so chip-bump pins read as BIDIRECT and a clock
+  // anchored on one propagates through the fat-net wire model on its own
+  // (no timing arc, no OpenSTA-private LibertyBuilder).
+  chip_master_lib_ = makeLibrary("3dic_chip_master_lib", "");
   for (dbChipInst* chip_inst : chip->getChipInsts()) {
     dbChip* master = chip_inst->getMasterChip();
     if (master == nullptr || chip_master_cells_.contains(master)) {
       continue;
     }
-    LibertyCell* lc
-        = builder.makeCell(chip_bump_lib_, master->getName(), "3dic-synth");
-    Cell* master_cell = reinterpret_cast<Cell*>(lc);
+    Cell* master_cell
+        = makeCell(chip_master_lib_, master->getName(), false, "");
     chip_master_cells_[master] = master_cell;
     for (odb::dbChipRegion* region : master->getChipRegions()) {
       for (odb::dbChipBump* bump : region->getChipBumps()) {
         odb::dbBTerm* bterm = bump->getBTerm();
         if (bterm == nullptr) {
           continue;
         }
-        LibertyPort* lp = builder.makePort(lc, bterm->getConstName());
-        lp->setDirection(dbToSta(bterm->getSigType(), bterm->getIoType()));
-        registerConcretePort(reinterpret_cast<Port*>(lp));
-        auto attrs = std::make_shared<TimingArcAttrs>();
-        attrs->setTimingType(TimingType::combinational);
-        lc->makeTimingArcSet(
-            lp, lp, nullptr, TimingRole::combinational(), attrs);
+        Port* port = makePort(master_cell, bterm->getConstName());
+        setDirection(port, dbToSta(bterm->getSigType(), bterm->getIoType()));
+        registerConcretePort(port);
       }
     }
-    lc->finish(false, report_, debug_);
   }
 }
 
@@ -1092,7 +1083,7 @@ void dbNetwork::clear()
   chip_bump_vertex_ids_.clear();
   block_to_chip_inst_.clear();
   block_disc_.clear();
-  chip_bump_lib_ = nullptr;
+  chip_master_lib_ = nullptr;
 }
 
 Instance* dbNetwork::topInstance() const

src/dbSta/test/3dic_cross.ok

@@ -32,10 +32,10 @@ Path Type: max
    0.09    0.09 ^ chipA/ff/Q (DFF_X1)
    0.01    0.09 v chipA/inv/ZN (INV_X1)
    0.02    0.11 v chipA/buf/Z (BUF_X1)
-   0.02    0.14 v chipB/buf/Z (BUF_X1)
-   0.01    0.15 ^ chipB/inv/ZN (INV_X1)
-   0.00    0.15 ^ chipB/ff/D (DFF_X1)
-           0.15   data arrival time
+   0.02    0.13 v chipB/buf/Z (BUF_X1)
+   0.01    0.14 ^ chipB/inv/ZN (INV_X1)
+   0.00    0.14 ^ chipB/ff/D (DFF_X1)
+           0.14   data arrival time
 
    1.00    1.00   clock clk (rise edge)
    0.00    1.00   clock network delay (ideal)
@@ -45,9 +45,9 @@ Path Type: max
            0.97   data required time
 ---------------------------------------------------------
            0.97   data required time
-          -0.15   data arrival time
+          -0.14   data arrival time
 ---------------------------------------------------------
-           0.82   slack (MET)
+           0.83   slack (MET)
 
 
 Summary 2 / 2 (100% pass)

src/dbSta/test/3dic_cross.tcl

@@ -32,8 +32,11 @@ check "bridge spans both chiplets" {
 } {chipA chipB}
 
 # Anchor the clock on the chip-bump pins of clk_top — the natural form
-# users will write. Propagation through the BIDIRECT bump relies on the
-# synthesized LibertyCell self-arc built in makeTopCellForChip.
+# users will write. Each chip-bump pin reports BIDIRECT (dbNetwork::
+# direction), so Graph::makePinVertices gives it both a load and a driver
+# vertex and create_clock seeds the arrival on both. The driver vertex then
+# fans out into the chiplet body via the fat-net wire-edge model, so the
+# clock reaches each chiplet's internal CK with no synthesized timing arc.
 create_clock -name clk -period 1.0 \
   [get_pins -of_objects [get_nets clk_top]]
 report_checks -path_delay max -group_path_count 4