Added description of inserted inst name prefixes

Incorporated review feedback

Signed-off-by: Jeff Ng <[email protected]>

Author: jeffng-or

src/cts/README.md

@@ -91,6 +91,16 @@ clock_tree_synthesis
 | `-delay_buffer_derate` | This option balances latencies between macro cells and registers by inserting delay buffers.  The default value is `1.0`, meaning all needed delay buffers are inserted.  A value of 0.5 means only half of necessary delay buffers are inserted.  A value of 0.0 means no insertion of delay buffers. |
 | `-library` | This option specifies the name of library from which clock buffers will be selected, such as the LVT or uLVT library.  It is assumed that the library has already been loaded using the read_liberty command.  If this option is not specified, clock buffers will be chosen from the currently loaded libraries, which may not include LVT or uLVT cells. |
 
+#### Instance Name Prefixes
+
+`clock_tree_synthesis` uses the following prefixes for the instances that it inserts:
+
+| Instance Prefix | Purpose |
+| ----- | ----- |
+| clkbuf_regs | Splitting registers from macros |
+| clkload | Dummy loads to help balance the clock tree |
+| delaybuf | Delay buffers to help balance the tree |
+
 ### Report CTS
 
 This command is used to extract the following metrics after a successful `clock_tree_synthesis` run. 

src/rsz/README.md

@@ -209,6 +209,15 @@ buffer_ports
 | `-inputs`, `-outputs` | Insert a buffer between the input and load, output and load respectively. The default behavior is `-inputs` and `-outputs` set if neither is specified. |
 | `-max_utilization` | Defines the percentage of core area used. |
 
+#### Instance Name Prefixes
+
+`buffer_ports` uses the following prefixes for the buffer instances that it inserts:
+
+| Instance Prefix | Purpose |
+| ----- | ----- |
+| input | Buffering primary inputs |
+| output | Buffering primary outputs |
+
 ### Remove Buffers
 
 Use the `remove_buffers` command to remove buffers inserted by synthesis. This
@@ -267,6 +276,19 @@ repair_design
 | `-match_cell_footprint` | Obey the Liberty cell footprint when swapping gates. |
 | `-verbose` | Enable verbose logging on progress of the repair. |
 
+#### Instance Name Prefixes
+
+`repair_design` uses the following prefixes for the buffer instances that it inserts:
+
+| Instance Prefix | Purpose |
+| ----- | ----- |
+| fanout | Fixing max fanout |
+| gain | Gain based buffering |
+| load_slew | Fixing max transition violations |
+| max_cap | Fixing max capacitance |
+| max_length | Fixing max length |
+| wire | Repairs load slew, length, and max capacitance violations in net wire segment |
+
 ### Repair Tie Fanout
 
 The `repair_tie_fanout` command connects each tie high/low load to a copy
@@ -348,6 +370,17 @@ Use`-recover_power` to specify the percent of paths with positive slack which
 will be considered for gate resizing to save power. It is recommended that
 this option be used with global routing based parasitics. 
 
+#### Instance Name Prefixes
+
+`repair_timing` uses the following prefixes for the buffer and gate instances that it inserts:
+
+| Instance Prefix | Purpose |
+| ----- | ----- |
+| clone | Gate cloning |
+| hold | Hold fixing |
+| rebuffer | Buffering for setup fixing |
+| split | Split off non-critical loads behind a buffer to reduce load |
+
 ### Repair Clock Nets
 
 The `clock_tree_synthesis` command inserts a clock tree in the design