No pin access: Which step in the flow is supposed to fix them?

[chrisgeli]

Hello,

I'm trying to set up a new (proprietary) technology. As a first simple test, I'm trying to build the gcd example using it, but it is running into routing violations it hasn't been able to fix.

Part of my PDN_TCL file creates vertical power stripes in M2 connecting the horizontal M1 stripes underneath:

And as you can see in the image, the placer has put this cell right underneath one of those M2 stripes, leading to a pin access issue with the M1 wire coming out towards the left.

I'm wondering if

• the router would ever be able to fix this (it would have to move the cell) or
• this should've been fixed by the placer?

If this is the placer's job, I'm wondering what I'm missing from my setup to allow it to do that?

[maliberty]

The router does not move cells; it is a placement issue. Does you technology have very limited layers? Usually people avoid m2 stripes for just this reason.

[chrisgeli]

The router does not move cells; it is a placement issue

That's good to know, thanks for the quick response.

Usually people avoid m2 stripes for just this reason.

Understood. Maybe I'll change the configuration to use M4 for the vertical power stripes.

But I'm also curious about possible solutions in case I'll ever need to restrict routes to below M4... one idea would be to block placement of cells under M2 stripes, but I'm struggling to find a way to enumerate the stripes generated by the add_pdn_stripe command... or is there a better way?

[maliberty]

Ideally the placer would consider this situation and avoid placing cells under such straps automatically. You could script up a manual solution to put placement blockages under the straps. You would need to get familiar with the database API in tcl.

[chrisgeli]

I used the following code at the end of my PDN_TCL file to generate placement blockages under MET2 routes. This is technology-specific (as it refers to the tech LEF's layer name and a grow_x_dbu number I found necessary to avoid M2 spacing violations where vias are placed close to M2 stripes) as well as design-specific (as it refers power/ground names) but apart from those, it should be pretty generic.

set nstripes 0
set grow_x_dbu "200"
foreach netname {VSS VDD} {
  set net [$block findNet $netname]
  foreach swire [$net getSWires] {
    foreach wire [$swire getWires] {
      if {[$wire isVia] == 0 && [[$wire getTechLayer] getName] == "MET2"} {
        incr nstripes
        set rect [$wire getOct]
        set bbox_dbu [list \
          [expr [$rect xMin] - $grow_x_dbu] \
          [$rect yMin] \
          [expr [$rect xMax] + $grow_x_dbu] \
          [$rect yMax]]
        puts "Creating placement blockage for $netname stripe at $bbox_dbu"
        set bbox [lmap n $bbox_dbu { expr {$n / $units} }]
        puts "Creating placement blockage for $netname stripe at $bbox"
        set b [odb::dbBlockage_create $block  {*}$bbox_dbu]
      }
    }
  }
}
puts "Added $nstripes placement blockages under MET2 power routes"

If anyone has any feedback to make this more generic or otherwise better, please let me know.

[maliberty]

Nice. Were you able to get your design through with this?