Question about the clock tree on ihp-sg13g2

[mole99]

Hi! What I see in the clock tree is different from what I would expect.

So I created a simple design with two sinks and manually extended the clock tree for one sink with a chain of sg13g2_buf_1 and for the other sink a chain of alternating sg13g2_buf_1 and sg13g2_buf_16.

This is the clock tree:

On the left is the sink with alternating buffers, on the right the sink with just a chain of sg13g2_buf_1.

I would have expected the transition from sg13g2_buf_1 to sg13g2_buf_16 to take longer than from sg13g2_buf_1 to sg13g2_buf_1. This is the case.

Likewise, I would have expected the transition from sg13g2_buf_16 to sg13g2_buf_1 to be much faster than from sg13g2_buf_1 to sg13g2_buf_1. This is not the case, how come? Am I reading the clock tree wrong, or am I overlooking something else?

The reproducible for the design is attached:
clock_tree_reproducible.zip

Thanks!

[maliberty]

a large buffer is not necessarily faster for a small load such as you have in this little block

[mole99]

Oh! I guess my mistake was thinking that the sg13g2_buf_16 switches quickly.

But that depends on how fast the sg13g2_buf_16 crosses its threshold, and since it is driven by a sg13g2_buf_1, that is probably rather slow. That's why we have the repair_design command, got it :)