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Merge branch 'YosysHQ:main' into master
2 parents 2df3a55 + 6f9c515 commit 995044f

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17 files changed

+133
-49
lines changed

17 files changed

+133
-49
lines changed

Diff for: ‎.github/workflows/test-build.yml

+2
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,7 @@ jobs:
5656
mkdir build
5757
cd build
5858
make -f ../Makefile config-$CC
59+
echo 'SANITIZER = undefined' >> Makefile.conf
5960
make -f ../Makefile -j$procs ENABLE_LTO=1
6061
6162
- name: Log yosys-config output
@@ -82,6 +83,7 @@ jobs:
8283
if: needs.pre_job.outputs.should_skip != 'true'
8384
env:
8485
CC: clang
86+
UBSAN_OPTIONS: halt_on_error=1
8587
strategy:
8688
matrix:
8789
os: [ubuntu-latest, macos-latest]

Diff for: ‎.mailmap

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
1-
Marcelina Kościelnicka <[email protected]>
2-
Marcelina Kościelnicka <mwk@0x04.net> <[email protected]>
3-
Marcelina Kościelnicka <mwk@0x04.net> <[email protected]>
1+
Wanda Phinode <[email protected]> <[email protected]>
2+
Wanda Phinode <wanda@phinode.net> <[email protected]>
3+
Wanda Phinode <wanda@phinode.net> <[email protected]>
44
Claire Xenia Wolf <[email protected]> <[email protected]>
55
Claire Xenia Wolf <[email protected]> <[email protected]>
66
Claire Xenia Wolf <[email protected]> <[email protected]>

Diff for: ‎CHANGELOG

+6-1
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,14 @@
22
List of major changes and improvements between releases
33
=======================================================
44

5-
Yosys 0.49 .. Yosys 0.50-dev
5+
Yosys 0.50 .. Yosys 0.51-dev
66
--------------------------
77

8+
Yosys 0.49 .. Yosys 0.50
9+
--------------------------
10+
* Various
11+
- "write_verilog" emits "$check" cell names as labels.
12+
813
Yosys 0.48 .. Yosys 0.49
914
--------------------------
1015
* Various

Diff for: ‎Makefile

+2-3
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,7 @@ ifeq ($(OS), Haiku)
153153
CXXFLAGS += -D_DEFAULT_SOURCE
154154
endif
155155

156-
YOSYS_VER := 0.49+1
156+
YOSYS_VER := 0.50+0
157157

158158
# Note: We arrange for .gitcommit to contain the (short) commit hash in
159159
# tarballs generated with git-archive(1) using .gitattributes. The git repo
@@ -169,7 +169,7 @@ endif
169169
OBJS = kernel/version_$(GIT_REV).o
170170

171171
bumpversion:
172-
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 427b5a2.. | wc -l`/;" Makefile
172+
sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline b5170e1.. | wc -l`/;" Makefile
173173

174174
ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q)
175175

@@ -1054,7 +1054,6 @@ clean:
10541054
rm -f tests/svinterfaces/*.log_stdout tests/svinterfaces/*.log_stderr tests/svinterfaces/dut_result.txt tests/svinterfaces/reference_result.txt tests/svinterfaces/a.out tests/svinterfaces/*_syn.v tests/svinterfaces/*.diff
10551055
rm -f tests/tools/cmp_tbdata
10561056
-$(MAKE) -C docs clean
1057-
-$(MAKE) -C docs/images clean
10581057
rm -rf docs/source/cmd docs/util/__pycache__
10591058

10601059
clean-abc:

Diff for: ‎backends/json/json.cc

+1-1
Original file line numberDiff line numberDiff line change
@@ -408,7 +408,7 @@ struct JsonBackend : public Backend {
408408
log("\n");
409409
log("The \"offset\" and \"upto\" fields are skipped if their value would be 0.\n");
410410
log("They don't affect connection semantics, and are only used to preserve original\n");
411-
log("HDL bit indexing.");
411+
log("HDL bit indexing.\n");
412412
log("And <cell_details> is:\n");
413413
log("\n");
414414
log(" {\n");

Diff for: ‎backends/verilog/verilog_backend.cc

+12-5
Original file line numberDiff line numberDiff line change
@@ -1044,16 +1044,23 @@ void dump_cell_expr_print(std::ostream &f, std::string indent, const RTLIL::Cell
10441044
void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell *cell)
10451045
{
10461046
std::string flavor = cell->getParam(ID(FLAVOR)).decode_string();
1047+
std::string label = "";
1048+
if (cell->name.isPublic()) {
1049+
label = stringf("%s: ", id(cell->name).c_str());
1050+
}
1051+
10471052
if (flavor == "assert")
1048-
f << stringf("%s" "assert (", indent.c_str());
1053+
f << stringf("%s" "%s" "assert (", indent.c_str(), label.c_str());
10491054
else if (flavor == "assume")
1050-
f << stringf("%s" "assume (", indent.c_str());
1055+
f << stringf("%s" "%s" "assume (", indent.c_str(), label.c_str());
10511056
else if (flavor == "live")
1052-
f << stringf("%s" "assert (eventually ", indent.c_str());
1057+
f << stringf("%s" "%s" "assert (eventually ", indent.c_str(), label.c_str());
10531058
else if (flavor == "fair")
1054-
f << stringf("%s" "assume (eventually ", indent.c_str());
1059+
f << stringf("%s" "%s" "assume (eventually ", indent.c_str(), label.c_str());
10551060
else if (flavor == "cover")
1056-
f << stringf("%s" "cover (", indent.c_str());
1061+
f << stringf("%s" "%s" "cover (", indent.c_str(), label.c_str());
1062+
else
1063+
log_abort();
10571064
dump_sigspec(f, cell->getPort(ID::A));
10581065
f << stringf(");\n");
10591066
}

Diff for: ‎docs/source/conf.py

+1-1
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
project = 'YosysHQ Yosys'
77
author = 'YosysHQ GmbH'
88
copyright ='2025 YosysHQ GmbH'
9-
yosys_ver = "0.49"
9+
yosys_ver = "0.50"
1010

1111
# select HTML theme
1212
html_theme = 'furo-ys'

Diff for: ‎frontends/ast/simplify.cc

+4-1
Original file line numberDiff line numberDiff line change
@@ -2936,7 +2936,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
29362936
lsb_expr->children[stride_ix]->detectSignWidth(stride_width, stride_sign);
29372937
max_width = std::max(i_width, stride_width);
29382938
// Stride width calculated from actual stride value.
2939-
stride_width = std::ceil(std::log2(std::abs(stride)));
2939+
if (stride == 0)
2940+
stride_width = 0;
2941+
else
2942+
stride_width = std::ceil(std::log2(std::abs(stride)));
29402943

29412944
if (i_width + stride_width > max_width) {
29422945
// For (truncated) i*stride to be within the range of dst, the following must hold:

Diff for: ‎kernel/celledges.cc

+3-3
Original file line numberDiff line numberDiff line change
@@ -253,13 +253,13 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
253253
if (a_width == 1 && is_signed) {
254254
int skip = 1 << (k + 1);
255255
int base = skip -1;
256-
if (i % skip != base && i - a_width + 2 < 1 << b_width)
256+
if (i % skip != base && i - a_width + 2 < 1 << b_width_capped)
257257
db->add_edge(cell, ID::B, k, ID::Y, i, -1);
258258
} else if (is_signed) {
259-
if (i - a_width + 2 < 1 << b_width)
259+
if (i - a_width + 2 < 1 << b_width_capped)
260260
db->add_edge(cell, ID::B, k, ID::Y, i, -1);
261261
} else {
262-
if (i - a_width + 1 < 1 << b_width)
262+
if (i - a_width + 1 < 1 << b_width_capped)
263263
db->add_edge(cell, ID::B, k, ID::Y, i, -1);
264264
}
265265
// right shifts

Diff for: ‎libs/fst/00_PATCH_strict_alignment.patch

+42
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
diff --git a/fastlz.cc b/fastlz.cc
2+
index 3272ca7a8..41ea27a16 100644
3+
--- a/fastlz.cc
4+
+++ b/fastlz.cc
5+
@@ -60,24 +60,9 @@
6+
#endif
7+
8+
/*
9+
- * Prevent accessing more than 8-bit at once, except on x86 architectures.
10+
+ * Yosys patch: do not do unaligned accesses on any platform
11+
*/
12+
-#if !defined(FASTLZ_STRICT_ALIGN)
13+
#define FASTLZ_STRICT_ALIGN
14+
-#if defined(__i386__) || defined(__386) /* GNU C, Sun Studio */
15+
-#undef FASTLZ_STRICT_ALIGN
16+
-#elif defined(__i486__) || defined(__i586__) || defined(__i686__) || defined(__amd64) /* GNU C */
17+
-#undef FASTLZ_STRICT_ALIGN
18+
-#elif defined(_M_IX86) /* Intel, MSVC */
19+
-#undef FASTLZ_STRICT_ALIGN
20+
-#elif defined(__386)
21+
-#undef FASTLZ_STRICT_ALIGN
22+
-#elif defined(_X86_) /* MinGW */
23+
-#undef FASTLZ_STRICT_ALIGN
24+
-#elif defined(__I86__) /* Digital Mars */
25+
-#undef FASTLZ_STRICT_ALIGN
26+
-#endif
27+
-#endif
28+
29+
/* prototypes */
30+
int fastlz_compress(const void* input, int length, void* output);
31+
@@ -88,11 +73,7 @@ int fastlz_decompress(const void* input, int length, void* output, int maxout);
32+
#define MAX_LEN 264 /* 256 + 8 */
33+
#define MAX_DISTANCE 8192
34+
35+
-#if !defined(FASTLZ_STRICT_ALIGN)
36+
-#define FASTLZ_READU16(p) *((const flzuint16*)(p))
37+
-#else
38+
#define FASTLZ_READU16(p) ((p)[0] | (p)[1]<<8)
39+
-#endif
40+
41+
#define HASH_LOG 13
42+
#define HASH_SIZE (1<< HASH_LOG)

Diff for: ‎libs/fst/00_UPDATE.sh

+1
Original file line numberDiff line numberDiff line change
@@ -17,3 +17,4 @@ sed -i -e 's,"fastlz.c","fastlz.cc",' *.cc *.h
1717

1818
patch -p0 < 00_PATCH_win_zlib.patch
1919
patch -p0 < 00_PATCH_win_io.patch
20+
patch -p1 < 00_PATCH_strict_alignment.patch

Diff for: ‎libs/fst/fastlz.cc

+1-20
Original file line numberDiff line numberDiff line change
@@ -60,24 +60,9 @@
6060
#endif
6161

6262
/*
63-
* Prevent accessing more than 8-bit at once, except on x86 architectures.
63+
* Yosys patch: do not do unaligned accesses on any platform
6464
*/
65-
#if !defined(FASTLZ_STRICT_ALIGN)
6665
#define FASTLZ_STRICT_ALIGN
67-
#if defined(__i386__) || defined(__386) /* GNU C, Sun Studio */
68-
#undef FASTLZ_STRICT_ALIGN
69-
#elif defined(__i486__) || defined(__i586__) || defined(__i686__) || defined(__amd64) /* GNU C */
70-
#undef FASTLZ_STRICT_ALIGN
71-
#elif defined(_M_IX86) /* Intel, MSVC */
72-
#undef FASTLZ_STRICT_ALIGN
73-
#elif defined(__386)
74-
#undef FASTLZ_STRICT_ALIGN
75-
#elif defined(_X86_) /* MinGW */
76-
#undef FASTLZ_STRICT_ALIGN
77-
#elif defined(__I86__) /* Digital Mars */
78-
#undef FASTLZ_STRICT_ALIGN
79-
#endif
80-
#endif
8166

8267
/* prototypes */
8368
int fastlz_compress(const void* input, int length, void* output);
@@ -88,11 +73,7 @@ int fastlz_decompress(const void* input, int length, void* output, int maxout);
8873
#define MAX_LEN 264 /* 256 + 8 */
8974
#define MAX_DISTANCE 8192
9075

91-
#if !defined(FASTLZ_STRICT_ALIGN)
92-
#define FASTLZ_READU16(p) *((const flzuint16*)(p))
93-
#else
9476
#define FASTLZ_READU16(p) ((p)[0] | (p)[1]<<8)
95-
#endif
9677

9778
#define HASH_LOG 13
9879
#define HASH_SIZE (1<< HASH_LOG)

Diff for: ‎passes/opt/wreduce.cc

+1-1
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,7 @@ struct WreduceWorker
280280
{
281281
bool did_something = false;
282282

283-
if (!cell->type.in(config->supported_cell_types))
283+
if (!config->supported_cell_types.count(cell->type))
284284
return;
285285

286286
if (cell->type.in(ID($mux), ID($pmux)))

Diff for: ‎passes/techmap/alumacc.cc

+18-8
Original file line numberDiff line numberDiff line change
@@ -405,11 +405,6 @@ struct AlumaccWorker
405405
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
406406
RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
407407

408-
if (B < A && GetSize(B)) {
409-
cmp_less = !cmp_less;
410-
std::swap(A, B);
411-
}
412-
413408
alunode_t *n = nullptr;
414409

415410
for (auto node : sig_alu[RTLIL::SigSig(A, B)])
@@ -418,6 +413,16 @@ struct AlumaccWorker
418413
break;
419414
}
420415

416+
if (n == nullptr) {
417+
for (auto node : sig_alu[RTLIL::SigSig(B, A)])
418+
if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
419+
n = node;
420+
cmp_less = !cmp_less;
421+
std::swap(A, B);
422+
break;
423+
}
424+
}
425+
421426
if (n == nullptr) {
422427
n = new alunode_t;
423428
n->a = A;
@@ -445,9 +450,6 @@ struct AlumaccWorker
445450
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
446451
RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
447452

448-
if (B < A && GetSize(B))
449-
std::swap(A, B);
450-
451453
alunode_t *n = nullptr;
452454

453455
for (auto node : sig_alu[RTLIL::SigSig(A, B)])
@@ -456,6 +458,14 @@ struct AlumaccWorker
456458
break;
457459
}
458460

461+
if (n == nullptr) {
462+
for (auto node : sig_alu[RTLIL::SigSig(B, A)])
463+
if (node->is_signed == is_signed && node->invert_b && node->c == State::S1) {
464+
n = node;
465+
break;
466+
}
467+
}
468+
459469
if (n != nullptr) {
460470
log(" creating $alu model for %s (%s): merged with %s.\n", log_id(cell), log_id(cell->type), log_id(n->cells.front()));
461471
n->cells.push_back(cell);

Diff for: ‎passes/techmap/extract_fa.cc

+3-2
Original file line numberDiff line numberDiff line change
@@ -412,14 +412,15 @@ struct ExtractFaWorker
412412
facache[fakey] = make_tuple(X, Y, cell);
413413
}
414414

415+
bool invert_y = f3i.inv_a ^ f3i.inv_b ^ f3i.inv_c;
415416
if (func3.at(key).count(xor3_func)) {
416-
SigBit YY = invert_xy ? module->NotGate(NEW_ID, Y) : Y;
417+
SigBit YY = invert_xy ^ invert_y ? module->NotGate(NEW_ID, Y) : Y;
417418
for (auto bit : func3.at(key).at(xor3_func))
418419
assign_new_driver(bit, YY);
419420
}
420421

421422
if (func3.at(key).count(xnor3_func)) {
422-
SigBit YY = invert_xy ? Y : module->NotGate(NEW_ID, Y);
423+
SigBit YY = invert_xy ^ invert_y ? Y : module->NotGate(NEW_ID, Y);
423424
for (auto bit : func3.at(key).at(xnor3_func))
424425
assign_new_driver(bit, YY);
425426
}

Diff for: ‎passes/techmap/libparse.h

+4
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,10 @@ namespace Yosys
5959

6060
std::string pin() {
6161
auto length = s.find_first_of("\t()'!^*& +|");
62+
if (length == std::string::npos) {
63+
// nothing found so use size of s
64+
length = s.size();
65+
}
6266
auto pin = s.substr(0, length);
6367
s = s.substr(length, s.size());
6468
return pin;

Diff for: ‎tests/various/bug3879.ys

+29
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
read_verilog <<EOF
2+
module gcd(I, D);
3+
4+
output [2:0] I;
5+
input [3:0] D;
6+
7+
assign I = D[0]+D[1]+D[2]+D[3];
8+
endmodule
9+
EOF
10+
design -save input
11+
12+
prep
13+
14+
design -stash gold
15+
16+
design -load input
17+
18+
synth -top gcd -flatten
19+
20+
extract_fa -v
21+
22+
design -stash gate
23+
24+
design -copy-from gold -as gold gcd
25+
design -copy-from gate -as gate gcd
26+
27+
miter -equiv -make_assert -flatten gold gate miter
28+
29+
sat -verify -prove-asserts -show-all miter

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