via layers should follow MOSIS design rules

[ericsmi]

The inverter below should not be legal as it allows the via layers to be used as de facto metal layers, which is not their intended function.

Recommended fix is to add the MOSIS DRC rules 14.1 to 14.5 to Siliwiz
https://www.ece.rice.edu/Courses/422/manual/mosis_scmos7_2.pdf

{
"version": 1,
"app": "siliwiz",
"timestamp": 1676395419,
"rects": [
{ "x": 8, "y": 2.94, "height": 383, "width": 384, "layer": "p substrate", "label": "" },
{ "x": 96, "y": 14.94, "height": 149, "width": 209, "layer": "n well" },
{ "x": 95.41, "y": 9.8, "height": 156, "width": 254, "layer": "n well" },
{ "x": 132, "y": 255.94, "height": 46, "width": 138, "layer": "n diffusion" },
{ "x": 132, "y": 70.94, "height": 62, "width": 138, "layer": "p diffusion" },
{ "x": 319.41, "y": 328.8, "height": 58, "width": 63, "layer": "p tap" },
{ "x": 291.41, "y": 25.8, "height": 52, "width": 47, "layer": "n tap" },
{ "x": 178, "y": 59.94, "height": 276, "width": 39, "layer": "polysilicon" },
{ "x": 148, "y": 166.94, "height": 41, "width": 53, "layer": "polysilicon" },
{ "x": 233, "y": 79.94, "height": 43, "width": 33, "layer": "metal1 via" },
{ "x": 132, "y": 74.94, "height": 53, "width": 37, "layer": "metal1 via" },
{ "x": 236, "y": 259.94, "height": 38, "width": 32, "layer": "metal1 via" },
{ "x": 132, "y": 258.94, "height": 40, "width": 34, "layer": "metal1 via" },
{ "x": 147, "y": 172.94, "height": 29, "width": 25, "layer": "metal1 via" },
{ "x": 295.41, "y": 22.8, "height": 34, "width": 40, "layer": "metal1 via" },
{ "x": 333.41, "y": 337.8, "height": 41, "width": 44, "layer": "metal1 via" },
{ "x": 39, "y": 168.94, "height": 39, "width": 88, "layer": "metal1", "label": "in" },
{ "x": 270, "y": 168.94, "height": 38, "width": 96, "layer": "metal1", "label": "out" },
{ "x": 229, "y": 79.94, "height": 218, "width": 41, "layer": "metal1" },
{ "x": 244, "y": 172.94, "height": 34, "width": 40, "layer": "metal1" },
{ "x": 128, "y": 20.94, "height": 102, "width": 36, "layer": "metal1" },
{ "x": 132, "y": 256.94, "height": 117, "width": 34, "layer": "metal1" },
{ "x": 40, "y": 337.94, "height": 40, "width": 334, "layer": "metal1" },
{ "x": 42, "y": 13.94, "height": 39, "width": 316, "layer": "metal1" },
{ "x": 29, "y": 9.94, "height": 49, "width": 51, "layer": "metal1", "label": "vdd" },
{ "x": 30, "y": 330.94, "height": 50, "width": 51, "layer": "metal1", "label": "vss" },
{ "x": 63.41, "y": 195, "height": 43, "width": 22, "layer": "metal2 via" },
{ "x": 87.41, "y": 233, "height": 10, "width": 85, "layer": "metal2 via" },
{ "x": 150.41, "y": 184, "height": 56, "width": 13, "layer": "metal2 via" },
{ "x": 48.41, "y": 225, "height": 25, "width": 69, "layer": "metal2" }
],
"graph": {
"dcSweep": false,
"minInVoltage": 0,
"maxInVoltage": 5,
"pulseDelay": 0,
"riseTime": 50,
"signalNames": "in out"
}
}