feat: update project tt_um_factory_test from TinyTapeout/tt08-factory-test

Commit: 2107fdb9fe4535da53beaab44d8f5b08afa2147b
Workflow: https://github.com/TinyTapeout/tt08-factory-test/actions/runs/9445358951

Author: TinyTapeoutBot

projects/tt_um_factory_test/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt08 3d87be1a",
+  "app": "Tiny Tapeout tt08 a4a87edf",
   "repo": "https://github.com/TinyTapeout/tt08-factory-test",
-  "commit": "1e92173e0f98b392b4e70465cd49f5dd3ec43cc4",
-  "workflow_url": "https://github.com/TinyTapeout/tt08-factory-test/actions/runs/9434432053",
+  "commit": "2107fdb9fe4535da53beaab44d8f5b08afa2147b",
+  "workflow_url": "https://github.com/TinyTapeout/tt08-factory-test/actions/runs/9445358951",
   "sort_id": 1718004568537,
   "openlane_version": "OpenLane2 2.0.8",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_factory_test/stats/metrics.csv

@@ -3,81 +3,81 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,310
-design__instance__area,1151.1
+design__instance__count,311
+design__instance__area,1161.11
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,1
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,5.548205808736384e-05
-power__switching__total,1.9140630683978088e-05
-power__leakage__total,2.256299147518348e-09
-power__total,7.462494249921292e-05
-clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.010983
-clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.010983
-timing__hold__ws__corner:nom_tt_025C_1v80,0.370715
-timing__setup__ws__corner:nom_tt_025C_1v80,10.825698
+power__internal__total,5.554137169383466e-05
+power__switching__total,2.0029066945426166e-05
+power__leakage__total,2.270782228919188e-09
+power__total,7.557270873803645e-05
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.002192
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.002192
+timing__hold__ws__corner:nom_tt_025C_1v80,0.403642
+timing__setup__ws__corner:nom_tt_025C_1v80,10.833368
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0.0
 timing__setup__wns__corner:nom_tt_025C_1v80,0.0
 timing__hold_vio__count__corner:nom_tt_025C_1v80,0
-timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.370715
+timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.403642
 timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
-timing__setup_r2r__ws__corner:nom_tt_025C_1v80,18.377371
+timing__setup_r2r__ws__corner:nom_tt_025C_1v80,17.926258
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
 design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:nom_ss_100C_1v60,1
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
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-clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.017005
-timing__hold__ws__corner:nom_ss_100C_1v60,0.971344
-timing__setup__ws__corner:nom_ss_100C_1v60,9.931769
+clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.002943
+clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.002943
+timing__hold__ws__corner:nom_ss_100C_1v60,1.039941
+timing__setup__ws__corner:nom_ss_100C_1v60,9.946104
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
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 timing__hold__wns__corner:nom_ss_100C_1v60,0.0
 timing__setup__wns__corner:nom_ss_100C_1v60,0.0
 timing__hold_vio__count__corner:nom_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.971344
+timing__hold_r2r__ws__corner:nom_ss_100C_1v60,1.039941
 timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
 timing__setup_vio__count__corner:nom_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:nom_ss_100C_1v60,16.854828
+timing__setup_r2r__ws__corner:nom_ss_100C_1v60,16.041178
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 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
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-clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.008191
-clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.008191
-timing__hold__ws__corner:nom_ff_n40C_1v95,0.144163
-timing__setup__ws__corner:nom_ff_n40C_1v95,11.178265
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.001685
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.001685
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.160183
+timing__setup__ws__corner:nom_ff_n40C_1v95,11.183133
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.144163
+timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.160183
 timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
-timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,18.865248
+timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,18.544693
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count,0
 design__max_fanout_violation__count,1
 design__max_cap_violation__count,0
-clock__skew__worst_hold,-0.007678
-clock__skew__worst_setup,-0.01793
-timing__hold__ws,0.137746
-timing__setup__ws,9.915246
+clock__skew__worst_hold,-0.001608
+clock__skew__worst_setup,-0.003137
+timing__hold__ws,0.154892
+timing__setup__ws,9.933782
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0.0
 timing__setup__wns,0.0
 timing__hold_vio__count,0
-timing__hold_r2r__ws,0.137746
+timing__hold_r2r__ws,0.154892
 timing__hold_r2r_vio__count,0
 timing__setup_vio__count,0
-timing__setup_r2r__ws,16.845661
+timing__setup_r2r__ws,16.022802
 timing__setup_r2r_vio__count,0
 design__die__bbox,0.0 0.0 161.0 111.52
 design__core__bbox,2.76 2.72 158.24 108.8
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,310
-design__instance__area__stdcell,1151.1
+design__instance__count__stdcell,311
+design__instance__area__stdcell,1161.11
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.0697921
-design__instance__utilization__stdcell,0.0697921
+design__instance__utilization,0.070399
+design__instance__utilization__stdcell,0.070399
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count,0
@@ -100,31 +100,31 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,1892.93
+route__wirelength__estimated,1921.59
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,8
+design__instance__count__hold_buffer,9
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-route__net,104
+route__net,105
 route__net__special,2
-route__drc_errors__iter:1,59
-route__wirelength__iter:1,2012
-route__drc_errors__iter:2,16
-route__wirelength__iter:2,1938
-route__drc_errors__iter:3,8
-route__wirelength__iter:3,1940
+route__drc_errors__iter:1,74
+route__wirelength__iter:1,2132
+route__drc_errors__iter:2,2
+route__wirelength__iter:2,1987
+route__drc_errors__iter:3,3
+route__wirelength__iter:3,1994
 route__drc_errors__iter:4,0
-route__wirelength__iter:4,1942
+route__wirelength__iter:4,1999
 route__drc_errors,0
-route__wirelength,1942
-route__vias,583
-route__vias__singlecut,583
+route__wirelength,1999
+route__vias,576
+route__vias__singlecut,576
 route__vias__multicut,0
 design__disconnected_pin__count,1
 design__critical_disconnected_pin__count,0
-route__wirelength__max,139.18
+route__wirelength__max,120.75
 timing__unannotated_net__count__corner:nom_tt_025C_1v80,2
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
 timing__unannotated_net__count__corner:nom_ss_100C_1v60,2
@@ -134,128 +134,128 @@ timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,1
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
-clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.010321
-clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.010321
-timing__hold__ws__corner:min_tt_025C_1v80,0.360988
-timing__setup__ws__corner:min_tt_025C_1v80,10.834974
+clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.00212
+clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.00212
+timing__hold__ws__corner:min_tt_025C_1v80,0.395275
+timing__setup__ws__corner:min_tt_025C_1v80,10.841746
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
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 timing__setup__wns__corner:min_tt_025C_1v80,0.0
 timing__hold_vio__count__corner:min_tt_025C_1v80,0
-timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.360988
+timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.395275
 timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
-timing__setup_r2r__ws__corner:min_tt_025C_1v80,18.389803
+timing__setup_r2r__ws__corner:min_tt_025C_1v80,17.937256
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-timing__hold__ws__corner:min_ss_100C_1v60,0.954075
-timing__setup__ws__corner:min_ss_100C_1v60,9.947407
+clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.002876
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+timing__hold__ws__corner:min_ss_100C_1v60,1.025055
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+timing__hold_r2r__ws__corner:min_ss_100C_1v60,1.025055
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-timing__setup_r2r__ws__corner:min_ss_100C_1v60,16.866026
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-timing__hold__ws__corner:min_ff_n40C_1v95,0.137746
-timing__setup__ws__corner:min_ff_n40C_1v95,11.18465
+clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.001608
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-timing__setup_r2r__ws__corner:max_ff_n40C_1v95,18.858238
+timing__setup_r2r__ws__corner:max_ff_n40C_1v95,18.538065
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__unannotated_net__count__corner:max_ff_n40C_1v95,2
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
 timing__unannotated_net__count,2
 timing__unannotated_net_filtered__count,0
-design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79965
-design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79998
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000353393
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00041916
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000223624
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00041916
+design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79996
+design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000370778
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000423173
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000126861
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000423173
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.0000230999999999999990605605015847601180212222971022129058837890625
-ir__drop__worst,0.000353000000000000015154544286133386776782572269439697265625
+ir__drop__avg,0.00000137000000000000001212029608621545406776931486092507839202880859375
+ir__drop__worst,0.0000371000000000000005446164352829185872906236909329891204833984375
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0