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feat: update project tt_um_chip_rom from TinyTapeout/tt-chip-rom
Commit: e22570f04abf0fd86c947af862c72f491abb1716 Workflow: https://github.com/TinyTapeout/tt-chip-rom/actions/runs/9444423792
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{
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"app": "Tiny Tapeout tt07 11b2d371",
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"app": "Tiny Tapeout tt08 a4a87edf",
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"repo": "https://github.com/TinyTapeout/tt-chip-rom",
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"commit": "7b1d3638536711cabd8fd4d131e10a37cdd208df",
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"workflow_url": "https://github.com/TinyTapeout/tt-chip-rom/actions/runs/9287983026",
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"sort_id": 1713709041187,
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"openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
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"pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"
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"commit": "e22570f04abf0fd86c947af862c72f491abb1716",
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"workflow_url": "https://github.com/TinyTapeout/tt-chip-rom/actions/runs/9444423792",
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"sort_id": 1718006002578,
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"openlane_version": "OpenLane2 2.0.8",
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"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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}
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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
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timing__unannotated_net__count,27
245+
timing__unannotated_net_filtered__count,0
246+
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79997
247+
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
248+
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000033554
249+
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000156404
250+
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,5.28195E-7
251+
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000156404
252+
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
253+
ir__drop__avg,9.71999999999999968720658903575948528441585949622094631195068359375E-7
254+
ir__drop__worst,0.0000335999999999999967854706628411776136999833397567272186279296875
255+
magic__drc_error__count,0
256+
magic__illegal_overlap__count,0
257+
design__lvs_device_difference__count,0
258+
design__lvs_net_difference__count,0
259+
design__lvs_property_fail__count,0
260+
design__lvs_error__count,0
261+
design__lvs_unmatched_device__count,0
262+
design__lvs_unmatched_net__count,0
263+
design__lvs_unmatched_pin__count,0
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,4 @@
1-
2-
63. Printing statistics.
1+
61. Printing statistics.
32

43
=== tt_um_chip_rom ===
54

@@ -11,7 +10,7 @@
1110
Number of memory bits: 0
1211
Number of processes: 0
1312
Number of cells: 24
14-
sky130_fd_sc_hd__conb_1 24
13+
sky130_fd_sc_hd__buf_2 24
1514

16-
Chip area for module '\tt_um_chip_rom': 90.086400
15+
Chip area for module '\tt_um_chip_rom': 120.115200
1716

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