@@ -3,81 +3,81 @@ design__lint_error__count,0
3
3
design__lint_timing_construct__count,0
4
4
design__lint_warning__count,2
5
5
design__inferred_latch__count,0
6
- design__instance__count,698
7
- design__instance__area,4665.72
6
+ design__instance__count,835
7
+ design__instance__area,5943.2
8
8
design__instance_unmapped__count,0
9
9
synthesis__check_error__count,0
10
10
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
11
- design__max_fanout_violation__count__corner:nom_tt_025C_1v80,2
11
+ design__max_fanout_violation__count__corner:nom_tt_025C_1v80,5
12
12
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
13
- power__internal__total,0.00026248395442962646
14
- power__switching__total,8.254130807472393e-05
15
- power__leakage__total,5.90233728559042e -09
16
- power__total,0.0003450311778578907
17
- clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.020609
18
- clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.020609
19
- timing__hold__ws__corner:nom_tt_025C_1v80,0.322891
20
- timing__setup__ws__corner:nom_tt_025C_1v80,10.467117
13
+ power__internal__total,0.00033680262276902795
14
+ power__switching__total,0.00013537477934733033
15
+ power__leakage__total,7.283217140496845e -09
16
+ power__total,0.00047218467807397246
17
+ clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.011986
18
+ clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.011986
19
+ timing__hold__ws__corner:nom_tt_025C_1v80,0.327012
20
+ timing__setup__ws__corner:nom_tt_025C_1v80,9.857509
21
21
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
22
22
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
23
23
timing__hold__wns__corner:nom_tt_025C_1v80,0.0
24
24
timing__setup__wns__corner:nom_tt_025C_1v80,0.0
25
25
timing__hold_vio__count__corner:nom_tt_025C_1v80,0
26
- timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.322891
26
+ timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.327012
27
27
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
28
28
timing__setup_vio__count__corner:nom_tt_025C_1v80,0
29
- timing__setup_r2r__ws__corner:nom_tt_025C_1v80,17.635612
29
+ timing__setup_r2r__ws__corner:nom_tt_025C_1v80,17.877186
30
30
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
31
- design__max_slew_violation__count__corner:nom_ss_100C_1v60,0
32
- design__max_fanout_violation__count__corner:nom_ss_100C_1v60,2
31
+ design__max_slew_violation__count__corner:nom_ss_100C_1v60,2
32
+ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,5
33
33
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
34
- clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.031218
35
- clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.031218
36
- timing__hold__ws__corner:nom_ss_100C_1v60,0.851092
37
- timing__setup__ws__corner:nom_ss_100C_1v60,9.210488
34
+ clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.020114
35
+ clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.020114
36
+ timing__hold__ws__corner:nom_ss_100C_1v60,0.88284
37
+ timing__setup__ws__corner:nom_ss_100C_1v60,8.024888
38
38
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
39
39
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
40
40
timing__hold__wns__corner:nom_ss_100C_1v60,0.0
41
41
timing__setup__wns__corner:nom_ss_100C_1v60,0.0
42
42
timing__hold_vio__count__corner:nom_ss_100C_1v60,0
43
- timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.851092
43
+ timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.88284
44
44
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
45
45
timing__setup_vio__count__corner:nom_ss_100C_1v60,0
46
- timing__setup_r2r__ws__corner:nom_ss_100C_1v60,13.313083
46
+ timing__setup_r2r__ws__corner:nom_ss_100C_1v60,13.932044
47
47
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
48
48
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
49
- design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,2
49
+ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,5
50
50
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
51
- clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.01611
52
- clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.01611
53
- timing__hold__ws__corner:nom_ff_n40C_1v95,0.11841
54
- timing__setup__ws__corner:nom_ff_n40C_1v95,10.943543
51
+ clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.009878
52
+ clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.009878
53
+ timing__hold__ws__corner:nom_ff_n40C_1v95,0.11978
54
+ timing__setup__ws__corner:nom_ff_n40C_1v95,10.55729
55
55
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
56
56
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
57
57
timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
58
58
timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
59
59
timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
60
- timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.11841
60
+ timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.11978
61
61
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
62
62
timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
63
- timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,18.430151
63
+ timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,18.589054
64
64
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
65
- design__max_slew_violation__count,0
66
- design__max_fanout_violation__count,2
65
+ design__max_slew_violation__count,2
66
+ design__max_fanout_violation__count,5
67
67
design__max_cap_violation__count,0
68
- clock__skew__worst_hold,-0.015499
69
- clock__skew__worst_setup,-0.033169
70
- timing__hold__ws,0.115588
71
- timing__setup__ws,9.187856
68
+ clock__skew__worst_hold,-0.009124
69
+ clock__skew__worst_setup,-0.022391
70
+ timing__hold__ws,0.116447
71
+ timing__setup__ws,7.983994
72
72
timing__hold__tns,0.0
73
73
timing__setup__tns,0.0
74
74
timing__hold__wns,0.0
75
75
timing__setup__wns,0.0
76
76
timing__hold_vio__count,0
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- timing__hold_r2r__ws,0.115588
77
+ timing__hold_r2r__ws,0.116447
78
78
timing__hold_r2r_vio__count,0
79
79
timing__setup_vio__count,0
80
- timing__setup_r2r__ws,13.266687
80
+ timing__setup_r2r__ws,13.878508
81
81
timing__setup_r2r_vio__count,0
82
82
design__die__bbox,0.0 0.0 161.0 111.52
83
83
design__core__bbox,2.76 2.72 158.24 108.8
@@ -86,12 +86,12 @@ flow__errors__count,0
86
86
design__io,45
87
87
design__die__area,17954.7
88
88
design__core__area,16493.3
89
- design__instance__count__stdcell,698
90
- design__instance__area__stdcell,4665.72
89
+ design__instance__count__stdcell,835
90
+ design__instance__area__stdcell,5943.2
91
91
design__instance__count__macros,0
92
92
design__instance__area__macros,0
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- design__instance__utilization,0.282886
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- design__instance__utilization__stdcell,0.282886
93
+ design__instance__utilization,0.36034
94
+ design__instance__utilization__stdcell,0.36034
95
95
design__power_grid_violation__count__net:VGND,0
96
96
design__power_grid_violation__count__net:VPWR,0
97
97
design__power_grid_violation__count,0
@@ -100,162 +100,164 @@ timing__drv__floating__pins,0
100
100
design__instance__displacement__total,0
101
101
design__instance__displacement__mean,0
102
102
design__instance__displacement__max,0
103
- route__wirelength__estimated,8028.47
103
+ route__wirelength__estimated,11176.7
104
104
design__violations,0
105
105
design__instance__count__setup_buffer,0
106
- design__instance__count__hold_buffer,29
106
+ design__instance__count__hold_buffer,46
107
107
antenna__violating__nets,0
108
108
antenna__violating__pins,0
109
109
route__antenna_violation__count,0
110
- route__net,492
110
+ route__net,629
111
111
route__net__special,2
112
- route__drc_errors__iter:1,238
113
- route__wirelength__iter:1,8982
114
- route__drc_errors__iter:2,70
115
- route__wirelength__iter:2,8934
116
- route__drc_errors__iter:3,116
117
- route__wirelength__iter:3,8881
118
- route__drc_errors__iter:4,0
119
- route__wirelength__iter:4,8864
112
+ route__drc_errors__iter:1,408
113
+ route__wirelength__iter:1,12819
114
+ route__drc_errors__iter:2,128
115
+ route__wirelength__iter:2,12712
116
+ route__drc_errors__iter:3,114
117
+ route__wirelength__iter:3,12602
118
+ route__drc_errors__iter:4,19
119
+ route__wirelength__iter:4,12536
120
+ route__drc_errors__iter:5,0
121
+ route__wirelength__iter:5,12546
120
122
route__drc_errors,0
121
- route__wirelength,8864
122
- route__vias,3346
123
- route__vias__singlecut,3346
123
+ route__wirelength,12546
124
+ route__vias,4293
125
+ route__vias__singlecut,4293
124
126
route__vias__multicut,0
125
- design__disconnected_pin__count,15
127
+ design__disconnected_pin__count,14
126
128
design__critical_disconnected_pin__count,0
127
- route__wirelength__max,156.36
128
- timing__unannotated_net__count__corner:nom_tt_025C_1v80,23
129
+ route__wirelength__max,163.21
130
+ timing__unannotated_net__count__corner:nom_tt_025C_1v80,22
129
131
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
130
- timing__unannotated_net__count__corner:nom_ss_100C_1v60,23
132
+ timing__unannotated_net__count__corner:nom_ss_100C_1v60,22
131
133
timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
132
- timing__unannotated_net__count__corner:nom_ff_n40C_1v95,23
134
+ timing__unannotated_net__count__corner:nom_ff_n40C_1v95,22
133
135
timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
134
136
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
135
- design__max_fanout_violation__count__corner:min_tt_025C_1v80,2
137
+ design__max_fanout_violation__count__corner:min_tt_025C_1v80,5
136
138
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
137
- clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.019876
138
- clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.019876
139
- timing__hold__ws__corner:min_tt_025C_1v80,0.319221
140
- timing__setup__ws__corner:min_tt_025C_1v80,10.480609
139
+ clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.011067
140
+ clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.011067
141
+ timing__hold__ws__corner:min_tt_025C_1v80,0.319049
142
+ timing__setup__ws__corner:min_tt_025C_1v80,9.880923
141
143
timing__hold__tns__corner:min_tt_025C_1v80,0.0
142
144
timing__setup__tns__corner:min_tt_025C_1v80,0.0
143
145
timing__hold__wns__corner:min_tt_025C_1v80,0.0
144
146
timing__setup__wns__corner:min_tt_025C_1v80,0.0
145
147
timing__hold_vio__count__corner:min_tt_025C_1v80,0
146
- timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.319221
148
+ timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.319049
147
149
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
148
150
timing__setup_vio__count__corner:min_tt_025C_1v80,0
149
- timing__setup_r2r__ws__corner:min_tt_025C_1v80,17.658636
151
+ timing__setup_r2r__ws__corner:min_tt_025C_1v80,17.909576
150
152
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
151
- timing__unannotated_net__count__corner:min_tt_025C_1v80,23
153
+ timing__unannotated_net__count__corner:min_tt_025C_1v80,22
152
154
timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
153
- design__max_slew_violation__count__corner:min_ss_100C_1v60,0
154
- design__max_fanout_violation__count__corner:min_ss_100C_1v60,2
155
+ design__max_slew_violation__count__corner:min_ss_100C_1v60,2
156
+ design__max_fanout_violation__count__corner:min_ss_100C_1v60,5
155
157
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
156
- clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.030006
157
- clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.030006
158
- timing__hold__ws__corner:min_ss_100C_1v60,0.844906
159
- timing__setup__ws__corner:min_ss_100C_1v60,9.237399
158
+ clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.01896
159
+ clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.01896
160
+ timing__hold__ws__corner:min_ss_100C_1v60,0.868272
161
+ timing__setup__ws__corner:min_ss_100C_1v60,8.065259
160
162
timing__hold__tns__corner:min_ss_100C_1v60,0.0
161
163
timing__setup__tns__corner:min_ss_100C_1v60,0.0
162
164
timing__hold__wns__corner:min_ss_100C_1v60,0.0
163
165
timing__setup__wns__corner:min_ss_100C_1v60,0.0
164
166
timing__hold_vio__count__corner:min_ss_100C_1v60,0
165
- timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.844906
167
+ timing__hold_r2r__ws__corner:min_ss_100C_1v60,0.868272
166
168
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
167
169
timing__setup_vio__count__corner:min_ss_100C_1v60,0
168
- timing__setup_r2r__ws__corner:min_ss_100C_1v60,13.363222
170
+ timing__setup_r2r__ws__corner:min_ss_100C_1v60,14.002484
169
171
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
170
- timing__unannotated_net__count__corner:min_ss_100C_1v60,23
172
+ timing__unannotated_net__count__corner:min_ss_100C_1v60,22
171
173
timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
172
174
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
173
- design__max_fanout_violation__count__corner:min_ff_n40C_1v95,2
175
+ design__max_fanout_violation__count__corner:min_ff_n40C_1v95,5
174
176
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
175
- clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.015499
176
- clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.015499
177
- timing__hold__ws__corner:min_ff_n40C_1v95,0.115588
178
- timing__setup__ws__corner:min_ff_n40C_1v95,10.953238
177
+ clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.009124
178
+ clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.009124
179
+ timing__hold__ws__corner:min_ff_n40C_1v95,0.116447
180
+ timing__setup__ws__corner:min_ff_n40C_1v95,10.572297
179
181
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
180
182
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
181
183
timing__hold__wns__corner:min_ff_n40C_1v95,0.0
182
184
timing__setup__wns__corner:min_ff_n40C_1v95,0.0
183
185
timing__hold_vio__count__corner:min_ff_n40C_1v95,0
184
- timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.115588
186
+ timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.116447
185
187
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
186
188
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
187
- timing__setup_r2r__ws__corner:min_ff_n40C_1v95,18.446758
189
+ timing__setup_r2r__ws__corner:min_ff_n40C_1v95,18.610039
188
190
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
189
- timing__unannotated_net__count__corner:min_ff_n40C_1v95,23
191
+ timing__unannotated_net__count__corner:min_ff_n40C_1v95,22
190
192
timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
191
193
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
192
- design__max_fanout_violation__count__corner:max_tt_025C_1v80,2
194
+ design__max_fanout_violation__count__corner:max_tt_025C_1v80,5
193
195
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
194
- clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.022058
195
- clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.022058
196
- timing__hold__ws__corner:max_tt_025C_1v80,0.327094
197
- timing__setup__ws__corner:max_tt_025C_1v80,10.455395
196
+ clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.013836
197
+ clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.013836
198
+ timing__hold__ws__corner:max_tt_025C_1v80,0.334896
199
+ timing__setup__ws__corner:max_tt_025C_1v80,9.834059
198
200
timing__hold__tns__corner:max_tt_025C_1v80,0.0
199
201
timing__setup__tns__corner:max_tt_025C_1v80,0.0
200
202
timing__hold__wns__corner:max_tt_025C_1v80,0.0
201
203
timing__setup__wns__corner:max_tt_025C_1v80,0.0
202
204
timing__hold_vio__count__corner:max_tt_025C_1v80,0
203
- timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.327094
205
+ timing__hold_r2r__ws__corner:max_tt_025C_1v80,0.334896
204
206
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
205
207
timing__setup_vio__count__corner:max_tt_025C_1v80,0
206
- timing__setup_r2r__ws__corner:max_tt_025C_1v80,17.6147
208
+ timing__setup_r2r__ws__corner:max_tt_025C_1v80,17.848455
207
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timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
208
- timing__unannotated_net__count__corner:max_tt_025C_1v80,23
210
+ timing__unannotated_net__count__corner:max_tt_025C_1v80,22
209
211
timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
210
- design__max_slew_violation__count__corner:max_ss_100C_1v60,0
211
- design__max_fanout_violation__count__corner:max_ss_100C_1v60,2
212
+ design__max_slew_violation__count__corner:max_ss_100C_1v60,2
213
+ design__max_fanout_violation__count__corner:max_ss_100C_1v60,5
212
214
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
213
- clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.033169
214
- clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.033169
215
- timing__hold__ws__corner:max_ss_100C_1v60,0.858453
216
- timing__setup__ws__corner:max_ss_100C_1v60,9.187856
215
+ clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.022391
216
+ clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.022391
217
+ timing__hold__ws__corner:max_ss_100C_1v60,0.89575
218
+ timing__setup__ws__corner:max_ss_100C_1v60,7.983994
217
219
timing__hold__tns__corner:max_ss_100C_1v60,0.0
218
220
timing__setup__tns__corner:max_ss_100C_1v60,0.0
219
221
timing__hold__wns__corner:max_ss_100C_1v60,0.0
220
222
timing__setup__wns__corner:max_ss_100C_1v60,0.0
221
223
timing__hold_vio__count__corner:max_ss_100C_1v60,0
222
- timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.858453
224
+ timing__hold_r2r__ws__corner:max_ss_100C_1v60,0.89575
223
225
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
224
226
timing__setup_vio__count__corner:max_ss_100C_1v60,0
225
- timing__setup_r2r__ws__corner:max_ss_100C_1v60,13.266687
227
+ timing__setup_r2r__ws__corner:max_ss_100C_1v60,13.878508
226
228
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
227
- timing__unannotated_net__count__corner:max_ss_100C_1v60,23
229
+ timing__unannotated_net__count__corner:max_ss_100C_1v60,22
228
230
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
229
231
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
230
- design__max_fanout_violation__count__corner:max_ff_n40C_1v95,2
232
+ design__max_fanout_violation__count__corner:max_ff_n40C_1v95,5
231
233
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
232
- clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.017506
233
- clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.017506
234
- timing__hold__ws__corner:max_ff_n40C_1v95,0.120941
235
- timing__setup__ws__corner:max_ff_n40C_1v95,10.934715
234
+ clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.011572
235
+ clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.011572
236
+ timing__hold__ws__corner:max_ff_n40C_1v95,0.122682
237
+ timing__setup__ws__corner:max_ff_n40C_1v95,10.541613
236
238
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
237
239
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
238
240
timing__hold__wns__corner:max_ff_n40C_1v95,0.0
239
241
timing__setup__wns__corner:max_ff_n40C_1v95,0.0
240
242
timing__hold_vio__count__corner:max_ff_n40C_1v95,0
241
- timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.120941
243
+ timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.122682
242
244
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
243
245
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
244
- timing__setup_r2r__ws__corner:max_ff_n40C_1v95,18.41543
246
+ timing__setup_r2r__ws__corner:max_ff_n40C_1v95,18.570307
245
247
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
246
- timing__unannotated_net__count__corner:max_ff_n40C_1v95,23
248
+ timing__unannotated_net__count__corner:max_ff_n40C_1v95,22
247
249
timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
248
- timing__unannotated_net__count,23
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+ timing__unannotated_net__count,22
249
251
timing__unannotated_net_filtered__count,0
250
- design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79996
252
+ design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79993
251
253
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
252
- design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000043499
253
- design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000521444
254
- design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000602537
255
- design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000521444
254
+ design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000678894
255
+ design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000439756
256
+ design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000809919
257
+ design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000439756
256
258
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
257
- ir__drop__avg,0.000005650000000000000114903746240013759916109847836196422576904296875
258
- ir__drop__worst,0.00004350000000000000025500435096859064287855289876461029052734375
259
+ ir__drop__avg,0.000008130000000000000087382358293641715363264665938913822174072265625
260
+ ir__drop__worst,0.00006789999999999999703327591138446450713672675192356109619140625
259
261
magic__drc_error__count,0
260
262
magic__illegal_overlap__count,0
261
263
design__lvs_device_difference__count,0
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