feat: update project tt_um_strau0106_cpu from strau0106/tt-simple-viii

Commit: ca5a5a33cbe9030921bcb561115a6bbde4b79baa
Workflow: https://github.com/strau0106/tt-simple-viii/actions/runs/13474682988

Author: TinyTapeoutBot

projects/tt_um_strau0106_cpu/commit_id.json

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+{
+  "app": "Tiny Tapeout tt10 022164a0",
+  "repo": "https://github.com/strau0106/tt-simple-viii",
+  "commit": "ca5a5a33cbe9030921bcb561115a6bbde4b79baa",
+  "workflow_url": "https://github.com/strau0106/tt-simple-viii/actions/runs/13474682988",
+  "sort_id": 1740242591256,
+  "openlane_version": "OpenLane2 2.2.9",
+  "pdk_version": "open_pdks 0fe599b2afb6708d281543108caf8310912f54af"
+}

projects/tt_um_strau0106_cpu/docs/info.md

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+<!---
+
+This file is used to generate your project datasheet. Please fill in the information below and delete any unused
+sections.
+
+You can also include images in this folder and reference them in the markdown. Each image must be less than
+512 kb in size, and the combined size of all images must be less than 1 MB.
+-->
+
+## How it works
+
+
+
+## How to test
+
+
+
+## External hardware
+
+

projects/tt_um_strau0106_cpu/info.yaml

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+# Tiny Tapeout project information
+project:
+  title:        "simlpe-viii"      # Project title
+  author:       "strau"      # Your name
+  discord:      "strau"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "A simple CPU Architecture"      # One line description of what your project does
+  language:     "SystemVerilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
+  top_module:  "tt_um_strau0106_cpu"
+
+  # List your project's source files here.
+  # Source files must be in ./src and you must list each source file separately, one per line.
+  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
+  source_files:
+    - "tt_um_strau0106_cpu.v"
+    - "packages/controlpack.sv"
+    - "modules/alu.sv"
+    - "modules/registers.sv"
+    - "modules/qspi_ctrl.v"
+    - "modules/mem_ctrl.sv"
+    - "units/mem.sv"
+    - "modules/ctrl.sv"
+    - "modules/mux.sv"
+    - "units/cpu.sv"
+
+# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
+pinout:
+  # Inputs
+  ui[0]: ""
+  ui[1]: ""
+  ui[2]: ""
+  ui[3]: ""
+  ui[4]: ""
+  ui[5]: ""
+  ui[6]: ""
+  ui[7]: ""
+
+  # Outputs
+  uo[0]: ""
+  uo[1]: ""
+  uo[2]: ""
+  uo[3]: ""
+  uo[4]: ""
+  uo[5]: ""
+  uo[6]: ""
+  uo[7]: ""
+
+  # Bidirectional pins
+  uio[0]: "cs flash"
+  uio[1]: "SD0"
+  uio[2]: "SD1"
+  uio[3]: "SCK"
+  uio[4]: "SD2"
+  uio[5]: "SD3"
+  uio[6]: "cs ram"
+  uio[7]: ""
+
+# Do not change!
+yaml_version: 6

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