feat: update project tt_um_alphaonesoc from alfadelta10010/tt10-AlphaOneSoC

Commit: 18651cbd7666840b0d7456334e7589c06ab8fb65
Workflow: https://github.com/alfadelta10010/tt10-AlphaOneSoC/actions/runs/13796164725

Author: TinyTapeoutBot

projects/tt_um_alphaonesoc/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt10 d89635e1",
+  "app": "Tiny Tapeout tt10 8f10bc8c",
   "repo": "https://github.com/alfadelta10010/tt10-AlphaOneSoC",
-  "commit": "4f3c6bba418d4a232479819145bb439e6271689a",
-  "workflow_url": "https://github.com/alfadelta10010/tt10-AlphaOneSoC/actions/runs/12445838248",
+  "commit": "18651cbd7666840b0d7456334e7589c06ab8fb65",
+  "workflow_url": "https://github.com/alfadelta10010/tt10-AlphaOneSoC/actions/runs/13796164725",
   "sort_id": 1734790698848,
   "openlane_version": "OpenLane2 2.2.9",
   "pdk_version": "open_pdks 0fe599b2afb6708d281543108caf8310912f54af"

projects/tt_um_alphaonesoc/docs/info.md

@@ -8,11 +8,12 @@ You can also include images in this folder and reference them in the markdown. E
 -->
 ## How it works
 
-A simple 32-bit RISC-V SoC, the project works by flashing the instruction code into the memory and observing the outputs over your desired method, via GPIO or UART
+A simple 32-bit RISC-V SoC on the RV32EC ISA, the project works by flashing the instruction code into the memory and observing the outputs over your desired method, via GPIO, UART or SPI
+The TT10-IHP submission is based entirely on MichaelBell's TinyQV from TT-06.
 
 ## How to test
 
 Flash the PMOD with instructions (somehow) and boot up the processor. The processor will start executing the instructions
 
 ## External hardware
-- [QSPI + Flash PMOD](https://github.com/mole99/qspi-pmod)
+- [QSPI + Flash PMOD](https://github.com/mole99/qspi-pmod)

projects/tt_um_alphaonesoc/info.yaml

@@ -3,9 +3,9 @@ project:
   title:        "AlphaOneSoC"
   author:       "Abhiram Gopal Dasika"
   discord:      "alfadelta10010"
-  description:  "A 32-bit General purpose SoC powered by RISC-V"      # One line description of what your project does
+  description:  "A 32-bit RISC-V SoC, based on TinyQV by Michael Bell"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     64000000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "2x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
@@ -16,40 +16,52 @@ project:
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
-  source_files:
+  source_files:        
     - "project.v"
+    - "tinyqv.v"
+    - "alu.v"
+    - "core.v"
+    - "counter.v"
+    - "cpu.v"
+    - "decode.v"
+    - "mem_ctrl.v"
+    - "qspi_ctrl.v"
+    - "register.v"
+    - "uart_tx.v"
+    - "uart_rx.v"
+    - "spi.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: "ui_in[0]"
-  ui[1]: "ui_in[1]"
-  ui[2]: "ui_in[2]"
-  ui[3]: "ui_in[3]"
-  ui[4]: "ui_in[4]"
-  ui[5]: "ui_in[5]"
-  ui[6]: "ui_in[6]"
-  ui[7]: "ui_in[7]"
+  ui[0]: "Interrupt 0"
+  ui[1]: "Interrupt 1"
+  ui[2]: "SPI MISO"
+  ui[3]: "GPI3"
+  ui[4]: "GPI4"
+  ui[5]: "GPI5"
+  ui[6]: "GPI6"
+  ui[7]: "UART RX"
 
   # Outputs
-  uo[0]: "uo_out[0]"
-  uo[1]: "uo_out[1]"
-  uo[2]: "uo_out[2]"
-  uo[3]: "uo_out[3]"
-  uo[4]: "uo_out[4]"
-  uo[5]: "uo_out[5]"
-  uo[6]: "uo_out[6]"
-  uo[7]: "uo_out[7]"
+  uo[0]: "UART TX"
+  uo[1]: "UART RTS"
+  uo[2]: "SPI DC"
+  uo[3]: "SPI MOSI"
+  uo[4]: "SPI CS"
+  uo[5]: "SPI SCK"
+  uo[6]: "Debug UART TX"
+  uo[7]: "Debug Signal"
 
   # Bidirectional pins
-  uio[0]: "uio_out[0], uio_in[0]"
-  uio[1]: "uio_out[1], uio_in[1]"
-  uio[2]: "uio_out[2], uio_in[2]"
-  uio[3]: "uio_out[3], uio_in[3]"
-  uio[4]: "uio_out[4], uio_in[4]"
-  uio[5]: "uio_out[5], uio_in[5]"
-  uio[6]: "uio_out[6], uio_in[6]"
-  uio[7]: "uio_out[7], uio_in[7]"
+  uio[0]: "Flash CS"
+  uio[1]: "SD0"
+  uio[2]: "SD1"
+  uio[3]: "SCK"
+  uio[4]: "SD2"
+  uio[5]: "SD3"
+  uio[6]: "RAM A CS"
+  uio[7]: "RAM B CS"
 
 # Do not change!
 yaml_version: 6