feat: update project tt_um_toivoh_demo from toivoh/tt10-demo

Commit: 058eb3df3fd5e949edc3a544b49dc09695d908f3
Workflow: https://github.com/toivoh/tt10-demo/actions/runs/13492014071

Author: TinyTapeoutBot

projects/tt_um_toivoh_demo/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt10 2036138b",
+  "app": "Tiny Tapeout tt10 8f10bc8c",
   "repo": "https://github.com/toivoh/tt10-demo",
-  "commit": "4373b7ca0196a03882684901ad752672fc8fcb6b",
-  "workflow_url": "https://github.com/toivoh/tt10-demo/actions/runs/12966645753",
+  "commit": "058eb3df3fd5e949edc3a544b49dc09695d908f3",
+  "workflow_url": "https://github.com/toivoh/tt10-demo/actions/runs/13492014071",
   "sort_id": 1737823564562,
   "openlane_version": "OpenLane2 2.2.9",
   "pdk_version": "open_pdks 0fe599b2afb6708d281543108caf8310912f54af"

projects/tt_um_toivoh_demo/info.yaml

@@ -1,25 +1,32 @@
 # Tiny Tapeout project information
 project:
-  title:        "TT10 demo"      # Project title
+  title:        "Orion Iron Ion [TT08 demo competition]"      # Project title
   author:       "Toivo Henningsson"      # Your name
   discord:      "possible_realities"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  "My contribution to the TT10 demo competition"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     50400000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+#  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_toivoh_demo"
+  top_module: "tt_um_toivoh_demo"
 
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
     - "project.v"
-    - "raster_scan.sv"
+    - "pwl4_synth.sv"
+    - "pwl4_player.sv"
     - "field_test.sv"
+    - "demo_top.sv"
+    - "afl2_alu.sv"
+    - "raster_scan.sv"
+    - "demo_control.sv"
+    - "logo_table_generated_c.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
@@ -30,8 +37,8 @@ pinout:
   ui[3]: ""
   ui[4]: ""
   ui[5]: ""
-  ui[6]: ""
-  ui[7]: ""
+  ui[6]: "advance[0]"
+  ui[7]: "advance[1]"
 
   # Outputs
   uo[0]: "R1"