feat: update project tt_um_multiplier from ChiranjitPatel/tt10-multiplier_UART_SPI

Commit: 009af0c6355df2d290fabad0c8dd5eb1e583795f
Workflow: https://github.com/ChiranjitPatel/tt10-multiplier_UART_SPI/actions/runs/13819275349

Author: TinyTapeoutBot

projects/tt_um_multiplier/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt10 0985eb1d",
+  "app": "Tiny Tapeout tt10 8f10bc8c",
   "repo": "https://github.com/ChiranjitPatel/tt10-multiplier_UART_SPI",
-  "commit": "14ee5897f55c6ca91b1c1f934b34a118d152eed8",
-  "workflow_url": "https://github.com/ChiranjitPatel/tt10-multiplier_UART_SPI/actions/runs/13268125144",
+  "commit": "009af0c6355df2d290fabad0c8dd5eb1e583795f",
+  "workflow_url": "https://github.com/ChiranjitPatel/tt10-multiplier_UART_SPI/actions/runs/13819275349",
   "sort_id": 1739292974090,
   "openlane_version": "OpenLane2 2.2.9",
   "pdk_version": "open_pdks 0fe599b2afb6708d281543108caf8310912f54af"

projects/tt_um_multiplier/docs/info.md

@@ -8,13 +8,20 @@ You can also include images in this folder and reference them in the markdown. E
 -->
 
 ## How it works
+This is a 8-bit binary multiplier
 
-This project is a binary vedic 8bit multiplier with UART and SPI
+Inputs:
+mul_ip_A
+mul_ip_B
+
+Ouputs:
+prod_low  
+prod_high
 
 ## How to test
+Give the two 8-bit inputs thorugh ui_in and uio_in. The multiplied data will be received at uo_out and uio_out
 
-This project is a binary vedic 8bit multiplier with UART and SPI
 
 ## External hardware
 
-None
+None

projects/tt_um_multiplier/info.yaml

@@ -12,21 +12,29 @@ project:
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
   top_module:  "tt_um_multiplier"
+  # top_module:  "tt_um_uart_spi"
 
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
     - "project.v"
-    - "i2bit_mul.sv"
-    - "i4bit_mul.sv"
-    - "i8bit_mul.sv"
     - "csa_1_4bit.sv"
-    - "csa_1_8bit.sv"
     - "csa_2_4bit.sv"
+    - "csa_1_8bit.sv"
     - "csa_2_8bit.sv"
-    - "fa.sv"
     - "ha.sv"
+    - "fa.sv"
+    - "i2bit_mul.sv"
+    - "i4bit_mul.sv"
+    - "i8bit_mul.sv"
+    
+    # - "uart_spi_top.sv"
+    # - "uart_rx_tx_loopback.sv"
+    # - "uart_rx.sv"
+    # - "uart_tx.sv"
+    # - "spi_slave.sv"
+ 
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:

projects/tt_um_multiplier/stats/metrics.csv

@@ -1,7 +1,7 @@
 Metric,Value
 design__lint_error__count,0
 design__lint_timing_construct__count,0
-design__lint_warning__count,4
+design__lint_warning__count,1
 design__inferred_latch__count,0
 design__instance__count,603
 design__instance__area,2710.1
@@ -10,14 +10,14 @@ synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.00007698713307036087
-power__switching__total,0.0001406994415447116
+power__internal__total,0.0000769906910136342
+power__switching__total,0.00014091368939261883
 power__leakage__total,3.6623257759771377E-9
-power__total,0.00021769024897366762
+power__total,0.0002179080474888906
 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
 timing__hold__ws__corner:nom_tt_025C_1v80,8.15838797388622
-timing__setup__ws__corner:nom_tt_025C_1v80,5.765122764579755
+timing__setup__ws__corner:nom_tt_025C_1v80,5.750453609385115
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -34,11 +34,11 @@ design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
 timing__hold__ws__corner:nom_ss_100C_1v60,8.489572840568972
-timing__setup__ws__corner:nom_ss_100C_1v60,-0.13156054396044764
+timing__setup__ws__corner:nom_ss_100C_1v60,-0.16254376082953204
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
-timing__setup__tns__corner:nom_ss_100C_1v60,-0.13156054396044764
+timing__setup__tns__corner:nom_ss_100C_1v60,-0.16254376082953204
 timing__hold__wns__corner:nom_ss_100C_1v60,0
-timing__setup__wns__corner:nom_ss_100C_1v60,-0.13156054396044764
+timing__setup__wns__corner:nom_ss_100C_1v60,-0.16254376082953204
 timing__hold_vio__count__corner:nom_ss_100C_1v60,0
 timing__hold_r2r__ws__corner:nom_ss_100C_1v60,Infinity
 timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
@@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
-timing__hold__ws__corner:nom_ff_n40C_1v95,7.973365304796752
-timing__setup__ws__corner:nom_ff_n40C_1v95,7.978074426911185
+timing__hold__ws__corner:nom_ff_n40C_1v95,7.973364416618307
+timing__setup__ws__corner:nom_ff_n40C_1v95,7.969132246328742
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -67,16 +67,16 @@ design__max_fanout_violation__count,0
 design__max_cap_violation__count,0
 clock__skew__worst_hold,0.0
 clock__skew__worst_setup,0.0
-timing__hold__ws,7.970422769609065
-timing__setup__ws,-0.2315339097093336
+timing__hold__ws,7.9704209932521755
+timing__setup__ws,-0.2631033243519989
 timing__hold__tns,0.0
-timing__setup__tns,-0.2315339097093336
+timing__setup__tns,-0.2696936084125598
 timing__hold__wns,0
-timing__setup__wns,-0.2315339097093336
+timing__setup__wns,-0.2631033243519989
 timing__hold_vio__count,0
 timing__hold_r2r__ws,inf
 timing__hold_r2r_vio__count,0
-timing__setup_vio__count,3
+timing__setup_vio__count,4
 timing__setup_r2r__ws,inf
 timing__setup_r2r_vio__count,0
 design__die__bbox,0.0 0.0 161.0 111.52
@@ -97,8 +97,8 @@ flow__warnings__count,1
 flow__errors__count,0
 design__instance__count__class:fill_cell,1426
 design__instance__count__class:tap_cell,225
-design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
+design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count,0
 timing__drv__floating__nets,0
 timing__drv__floating__pins,0
@@ -116,22 +116,22 @@ route__antenna_violation__count,0
 antenna_diodes_count,0
 route__net,397
 route__net__special,2
-route__drc_errors__iter:1,151
-route__wirelength__iter:1,6662
-route__drc_errors__iter:2,58
-route__wirelength__iter:2,6591
-route__drc_errors__iter:3,63
-route__wirelength__iter:3,6564
+route__drc_errors__iter:1,147
+route__wirelength__iter:1,6672
+route__drc_errors__iter:2,100
+route__wirelength__iter:2,6596
+route__drc_errors__iter:3,55
+route__wirelength__iter:3,6572
 route__drc_errors__iter:4,0
-route__wirelength__iter:4,6576
+route__wirelength__iter:4,6619
 route__drc_errors,0
-route__wirelength,6576
-route__vias,2412
-route__vias__singlecut,2412
+route__wirelength,6619
+route__vias,2426
+route__vias__singlecut,2426
 route__vias__multicut,0
 design__disconnected_pin__count,3
 design__critical_disconnected_pin__count,0
-route__wirelength__max,118.72
+route__wirelength__max,120.54
 timing__unannotated_net__count__corner:nom_tt_025C_1v80,11
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
 timing__unannotated_net__count__corner:nom_ss_100C_1v60,11
@@ -143,8 +143,8 @@ design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
-timing__hold__ws__corner:min_tt_025C_1v80,8.153900008204548
-timing__setup__ws__corner:min_tt_025C_1v80,5.823690139409599
+timing__hold__ws__corner:min_tt_025C_1v80,8.153900896382993
+timing__setup__ws__corner:min_tt_025C_1v80,5.811513212931123
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -163,11 +163,11 @@ design__max_cap_violation__count__corner:min_ss_100C_1v60,0
 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
 timing__hold__ws__corner:min_ss_100C_1v60,8.484489795329269
-timing__setup__ws__corner:min_ss_100C_1v60,-0.03374900454625239
+timing__setup__ws__corner:min_ss_100C_1v60,-0.05786304932310255
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
-timing__setup__tns__corner:min_ss_100C_1v60,-0.03374900454625239
+timing__setup__tns__corner:min_ss_100C_1v60,-0.05786304932310255
 timing__hold__wns__corner:min_ss_100C_1v60,0
-timing__setup__wns__corner:min_ss_100C_1v60,-0.03374900454625239
+timing__setup__wns__corner:min_ss_100C_1v60,-0.05786304932310255
 timing__hold_vio__count__corner:min_ss_100C_1v60,0
 timing__hold_r2r__ws__corner:min_ss_100C_1v60,Infinity
 timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
@@ -181,8 +181,8 @@ design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
-timing__hold__ws__corner:min_ff_n40C_1v95,7.970422769609065
-timing__setup__ws__corner:min_ff_n40C_1v95,8.020729196723643
+timing__hold__ws__corner:min_ff_n40C_1v95,7.9704209932521755
+timing__setup__ws__corner:min_ff_n40C_1v95,8.013946177940555
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -200,8 +200,8 @@ design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
-timing__hold__ws__corner:max_tt_025C_1v80,8.16216006774137
-timing__setup__ws__corner:max_tt_025C_1v80,5.709397560773333
+timing__hold__ws__corner:max_tt_025C_1v80,8.162160955919814
+timing__setup__ws__corner:max_tt_025C_1v80,5.694724852864914
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -220,15 +220,15 @@ design__max_cap_violation__count__corner:max_ss_100C_1v60,0
 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
 timing__hold__ws__corner:max_ss_100C_1v60,8.495824728642056
-timing__setup__ws__corner:max_ss_100C_1v60,-0.2315339097093336
+timing__setup__ws__corner:max_ss_100C_1v60,-0.2631033243519989
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
-timing__setup__tns__corner:max_ss_100C_1v60,-0.2315339097093336
+timing__setup__tns__corner:max_ss_100C_1v60,-0.2696936084125598
 timing__hold__wns__corner:max_ss_100C_1v60,0
-timing__setup__wns__corner:max_ss_100C_1v60,-0.2315339097093336
+timing__setup__wns__corner:max_ss_100C_1v60,-0.2631033243519989
 timing__hold_vio__count__corner:max_ss_100C_1v60,0
 timing__hold_r2r__ws__corner:max_ss_100C_1v60,Infinity
 timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
-timing__setup_vio__count__corner:max_ss_100C_1v60,1
+timing__setup_vio__count__corner:max_ss_100C_1v60,2
 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__unannotated_net__count__corner:max_ss_100C_1v60,11
@@ -238,8 +238,8 @@ design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
-timing__hold__ws__corner:max_ff_n40C_1v95,7.975870856189588
-timing__setup__ws__corner:max_ff_n40C_1v95,7.941312721080105
+timing__hold__ws__corner:max_ff_n40C_1v95,7.9758681916542535
+timing__setup__ws__corner:max_ff_n40C_1v95,7.932148495886457
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -256,18 +256,18 @@ timing__unannotated_net__count,11
 timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79994
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000614975
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000068176
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000385105
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000068176
-design_powergrid__voltage__worst,0.000068176
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000614987
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000679873
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000384048
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000679873
+design_powergrid__voltage__worst,0.0000679873
 design_powergrid__voltage__worst__net:VPWR,1.79994
-design_powergrid__drop__worst,0.000068176
-design_powergrid__drop__worst__net:VPWR,0.0000614975
-design_powergrid__voltage__worst__net:VGND,0.000068176
-design_powergrid__drop__worst__net:VGND,0.000068176
+design_powergrid__drop__worst,0.0000679873
+design_powergrid__drop__worst__net:VPWR,0.0000614987
+design_powergrid__voltage__worst__net:VGND,0.0000679873
+design_powergrid__drop__worst__net:VGND,0.0000679873
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.00000375000000000000009500321536404232602990305167622864246368408203125
+ir__drop__avg,0.00000375999999999999999925948991619240047157290973700582981109619140625
 ir__drop__worst,0.00006150000000000000409915157373319516409537754952907562255859375
 magic__drc_error__count,0
 magic__illegal_overlap__count,0

projects/tt_um_multiplier/tt_um_multiplier.gds

@@ -476,12 +476,12 @@ MACRO tt_um_multiplier
         RECT 133.490 110.120 135.150 111.170 ;
         RECT 136.250 110.120 137.910 111.170 ;
         RECT 30.655 109.440 138.625 110.120 ;
-        RECT 30.655 102.175 56.750 109.440 ;
-        RECT 59.150 102.175 60.050 109.440 ;
-        RECT 62.450 102.175 95.620 109.440 ;
-        RECT 98.020 102.175 98.920 109.440 ;
-        RECT 101.320 102.175 134.490 109.440 ;
-        RECT 136.890 102.175 137.790 109.440 ;
+        RECT 30.655 83.815 56.750 109.440 ;
+        RECT 59.150 83.815 60.050 109.440 ;
+        RECT 62.450 83.815 95.620 109.440 ;
+        RECT 98.020 83.815 98.920 109.440 ;
+        RECT 101.320 83.815 134.490 109.440 ;
+        RECT 136.890 83.815 137.790 109.440 ;
   END
 END tt_um_multiplier
 END LIBRARY