Skip to content

Commit ada307d

Browse files
TinyTapeoutBoturish
TinyTapeoutBot
authored and
urish
committed
feat: update project tt_um_UartMain from gantover/tt10-verilog-gantover
Commit: 7389825df6426002f9fa63078a4e7f790558e456 Workflow: https://github.com/gantover/tt10-verilog-gantover/actions/runs/13742092967
1 parent d381dd8 commit ada307d

File tree

9 files changed

+2432
-2330
lines changed

9 files changed

+2432
-2330
lines changed

‎projects/tt_um_UartMain/commit_id.json‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
{
22
"app": "Tiny Tapeout tt10 8f10bc8c",
33
"repo": "https://github.com/gantover/tt10-verilog-gantover",
4-
"commit": "0a16ab9c988dc0bae0598459e7119cbeaf1c4b30",
5-
"workflow_url": "https://github.com/gantover/tt10-verilog-gantover/actions/runs/13587227256",
4+
"commit": "7389825df6426002f9fa63078a4e7f790558e456",
5+
"workflow_url": "https://github.com/gantover/tt10-verilog-gantover/actions/runs/13742092967",
66
"sort_id": 1739633843909,
77
"openlane_version": "OpenLane2 2.2.9",
88
"pdk_version": "open_pdks 0fe599b2afb6708d281543108caf8310912f54af"

‎projects/tt_um_UartMain/docs/info.md‎

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -9,13 +9,25 @@ You can also include images in this folder and reference them in the markdown. E
99

1010
## How it works
1111

12-
It does not work
12+
You send a char via a uart port (8bit data, no partity bit) and it sends an "encrypted" char back
13+
14+
To update the key : briefly activate a 1 signal on updateKey port, the circuit will now wait for the next input and set it as the new key once received
15+
16+
> the activation signal for updateKey should be held down before sending the new key otherwise the circuit will stay in the updateKey state
17+
18+
The default key is b10101010.
1319

1420
## How to test
1521

16-
You cannot test it
22+
A python file containing a code to communicate with the serial port may be transformed to work with the TT board.
1723

1824
## External hardware
1925

20-
No external hardware used
21-
Trigger
26+
It requires an input clock of 50Mhz
27+
28+
It has two inputs :
29+
ui[0]: "updateKey"
30+
ui[7]: "rx"
31+
32+
and one output
33+
uo[0]: "tx"

‎projects/tt_um_UartMain/info.yaml‎

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,12 @@
11
# Tiny Tapeout project information
22
project:
3-
title: "empty for now" # Project title
3+
title: "XOR Cipher" # Project title
44
author: "Damian" # Your name
55
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
6-
description: "Does nothing" # One line description of what your project does
6+
description: "Simple XOR Cipher with UART" # One line description of what your project does
77
language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
8-
clock_hz: 10000000 # Clock frequency in Hz (or 0 if not applicable)
8+
clock_hz: 50000000
9+
# clock_hz: 10000000 # Clock frequency in Hz (or 0 if not applicable) 50000000
910

1011
# How many tiles your design occupies? A single tile is about 167x108 uM.
1112
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
@@ -22,17 +23,17 @@ project:
2223
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
2324
pinout:
2425
# Inputs
25-
ui[0]: "io_rxd"
26+
ui[0]: "updateKey"
2627
ui[1]: ""
2728
ui[2]: ""
2829
ui[3]: ""
2930
ui[4]: ""
3031
ui[5]: ""
3132
ui[6]: ""
32-
ui[7]: ""
33+
ui[7]: "rx"
3334

3435
# Outputs
35-
uo[0]: "io_txd"
36+
uo[0]: "tx"
3637
uo[1]: ""
3738
uo[2]: ""
3839
uo[3]: ""

‎projects/tt_um_UartMain/stats/metrics.csv‎

Lines changed: 123 additions & 123 deletions
Large diffs are not rendered by default.

‎projects/tt_um_UartMain/stats/synthesis-stats.txt‎

Lines changed: 38 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -2,51 +2,53 @@
22

33
=== tt_um_UartMain ===
44

5-
Number of wires: 314
6-
Number of wire bits: 349
7-
Number of public wires: 85
8-
Number of public wire bits: 120
5+
Number of wires: 342
6+
Number of wire bits: 377
7+
Number of public wires: 94
8+
Number of public wire bits: 129
99
Number of ports: 8
1010
Number of port bits: 43
1111
Number of memories: 0
1212
Number of memory bits: 0
1313
Number of processes: 0
14-
Number of cells: 330
15-
sky130_fd_sc_hd__a2111o_2 1
16-
sky130_fd_sc_hd__a211o_2 2
14+
Number of cells: 358
15+
sky130_fd_sc_hd__a211o_2 8
1716
sky130_fd_sc_hd__a211oi_2 1
17+
sky130_fd_sc_hd__a21bo_2 1
1818
sky130_fd_sc_hd__a21boi_2 1
19-
sky130_fd_sc_hd__a21o_2 14
20-
sky130_fd_sc_hd__a21oi_2 26
21-
sky130_fd_sc_hd__a31o_2 4
22-
sky130_fd_sc_hd__a41o_2 1
23-
sky130_fd_sc_hd__and2_2 1
24-
sky130_fd_sc_hd__and2b_2 1
25-
sky130_fd_sc_hd__and3_2 4
19+
sky130_fd_sc_hd__a21o_2 8
20+
sky130_fd_sc_hd__a21oi_2 29
21+
sky130_fd_sc_hd__a31o_2 6
22+
sky130_fd_sc_hd__and2_2 5
23+
sky130_fd_sc_hd__and2b_2 2
24+
sky130_fd_sc_hd__and3_2 3
2625
sky130_fd_sc_hd__buf_2 1
2726
sky130_fd_sc_hd__conb_1 23
28-
sky130_fd_sc_hd__dfxtp_2 77
29-
sky130_fd_sc_hd__inv_2 8
30-
sky130_fd_sc_hd__nand2_2 19
31-
sky130_fd_sc_hd__nand2b_2 1
32-
sky130_fd_sc_hd__nor2_2 18
33-
sky130_fd_sc_hd__nor3_2 4
34-
sky130_fd_sc_hd__nor4_2 2
35-
sky130_fd_sc_hd__o2111ai_2 1
36-
sky130_fd_sc_hd__o211a_2 19
37-
sky130_fd_sc_hd__o211ai_2 1
38-
sky130_fd_sc_hd__o21a_2 10
39-
sky130_fd_sc_hd__o21ai_2 10
40-
sky130_fd_sc_hd__o21ba_2 2
41-
sky130_fd_sc_hd__o221a_2 1
42-
sky130_fd_sc_hd__o22a_2 6
27+
sky130_fd_sc_hd__dfxtp_2 86
28+
sky130_fd_sc_hd__inv_2 4
29+
sky130_fd_sc_hd__mux2_1 1
30+
sky130_fd_sc_hd__nand2_2 18
31+
sky130_fd_sc_hd__nand2b_2 2
32+
sky130_fd_sc_hd__nor2_2 19
33+
sky130_fd_sc_hd__nor3_2 3
34+
sky130_fd_sc_hd__o211a_2 23
35+
sky130_fd_sc_hd__o21a_2 8
36+
sky130_fd_sc_hd__o21ai_2 11
37+
sky130_fd_sc_hd__o21ba_2 3
38+
sky130_fd_sc_hd__o221a_2 7
39+
sky130_fd_sc_hd__o22a_2 1
4340
sky130_fd_sc_hd__o2bb2a_2 1
44-
sky130_fd_sc_hd__o32a_2 1
45-
sky130_fd_sc_hd__or2_2 24
46-
sky130_fd_sc_hd__or3_2 23
47-
sky130_fd_sc_hd__or4_2 14
48-
sky130_fd_sc_hd__xor2_2 8
41+
sky130_fd_sc_hd__o311a_2 1
42+
sky130_fd_sc_hd__o31a_2 1
43+
sky130_fd_sc_hd__o31ai_2 2
44+
sky130_fd_sc_hd__or2_2 40
45+
sky130_fd_sc_hd__or3_2 9
46+
sky130_fd_sc_hd__or3b_2 1
47+
sky130_fd_sc_hd__or4_2 13
48+
sky130_fd_sc_hd__or4b_2 2
49+
sky130_fd_sc_hd__xnor2_2 1
50+
sky130_fd_sc_hd__xor2_2 13
4951

50-
Chip area for module '\tt_um_UartMain': 3645.996800
51-
of which used for sequential elements: 1637.820800 (44.92%)
52+
Chip area for module '\tt_um_UartMain': 4055.139200
53+
of which used for sequential elements: 1829.254400 (45.11%)
5254

‎projects/tt_um_UartMain/tt_um_UartMain.gds‎

34.2 KB
Binary file not shown.

‎projects/tt_um_UartMain/tt_um_UartMain.lef‎

Lines changed: 52 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,7 @@ MACRO tt_um_UartMain
133133
PIN ui_in[7]
134134
DIRECTION INPUT ;
135135
USE SIGNAL ;
136+
ANTENNAGATEAREA 0.196500 ;
136137
PORT
137138
LAYER met4 ;
138139
RECT 118.990 110.520 119.290 111.520 ;
@@ -403,59 +404,59 @@ MACRO tt_um_UartMain
403404
LAYER met1 ;
404405
RECT 2.760 2.480 158.240 109.040 ;
405406
LAYER met2 ;
406-
RECT 18.310 2.535 155.380 110.005 ;
407+
RECT 18.310 2.535 155.840 110.685 ;
407408
LAYER met3 ;
408-
RECT 18.290 2.555 144.370 109.985 ;
409-
LAYER met4 ;
410-
RECT 31.370 110.120 33.030 110.520 ;
411-
RECT 34.130 110.120 35.790 110.520 ;
412-
RECT 36.890 110.120 38.550 110.520 ;
413-
RECT 39.650 110.120 41.310 110.520 ;
414-
RECT 42.410 110.120 44.070 110.520 ;
415-
RECT 45.170 110.120 46.830 110.520 ;
416-
RECT 47.930 110.120 49.590 110.520 ;
417-
RECT 50.690 110.120 52.350 110.520 ;
418-
RECT 53.450 110.120 55.110 110.520 ;
419-
RECT 56.210 110.120 57.870 110.520 ;
420-
RECT 58.970 110.120 60.630 110.520 ;
421-
RECT 61.730 110.120 63.390 110.520 ;
422-
RECT 64.490 110.120 66.150 110.520 ;
423-
RECT 67.250 110.120 68.910 110.520 ;
424-
RECT 70.010 110.120 71.670 110.520 ;
425-
RECT 72.770 110.120 74.430 110.520 ;
426-
RECT 75.530 110.120 77.190 110.520 ;
427-
RECT 78.290 110.120 79.950 110.520 ;
428-
RECT 81.050 110.120 82.710 110.520 ;
429-
RECT 83.810 110.120 85.470 110.520 ;
430-
RECT 86.570 110.120 88.230 110.520 ;
431-
RECT 89.330 110.120 90.990 110.520 ;
432-
RECT 92.090 110.120 93.750 110.520 ;
433-
RECT 94.850 110.120 96.510 110.520 ;
434-
RECT 97.610 110.120 99.270 110.520 ;
435-
RECT 100.370 110.120 102.030 110.520 ;
436-
RECT 103.130 110.120 104.790 110.520 ;
437-
RECT 105.890 110.120 107.550 110.520 ;
438-
RECT 108.650 110.120 110.310 110.520 ;
439-
RECT 111.410 110.120 113.070 110.520 ;
440-
RECT 114.170 110.120 115.830 110.520 ;
441-
RECT 116.930 110.120 118.590 110.520 ;
442-
RECT 119.690 110.120 121.350 110.520 ;
443-
RECT 122.450 110.120 124.110 110.520 ;
444-
RECT 125.210 110.120 126.870 110.520 ;
445-
RECT 127.970 110.120 129.630 110.520 ;
446-
RECT 130.730 110.120 132.390 110.520 ;
447-
RECT 133.490 110.120 135.150 110.520 ;
448-
RECT 136.250 110.120 137.910 110.520 ;
449-
RECT 139.010 110.120 140.670 110.520 ;
450-
RECT 141.770 110.120 143.430 110.520 ;
409+
RECT 18.290 2.555 152.655 110.665 ;
410+
LAYER met4 ;
411+
RECT 31.370 110.120 33.030 110.665 ;
412+
RECT 34.130 110.120 35.790 110.665 ;
413+
RECT 36.890 110.120 38.550 110.665 ;
414+
RECT 39.650 110.120 41.310 110.665 ;
415+
RECT 42.410 110.120 44.070 110.665 ;
416+
RECT 45.170 110.120 46.830 110.665 ;
417+
RECT 47.930 110.120 49.590 110.665 ;
418+
RECT 50.690 110.120 52.350 110.665 ;
419+
RECT 53.450 110.120 55.110 110.665 ;
420+
RECT 56.210 110.120 57.870 110.665 ;
421+
RECT 58.970 110.120 60.630 110.665 ;
422+
RECT 61.730 110.120 63.390 110.665 ;
423+
RECT 64.490 110.120 66.150 110.665 ;
424+
RECT 67.250 110.120 68.910 110.665 ;
425+
RECT 70.010 110.120 71.670 110.665 ;
426+
RECT 72.770 110.120 74.430 110.665 ;
427+
RECT 75.530 110.120 77.190 110.665 ;
428+
RECT 78.290 110.120 79.950 110.665 ;
429+
RECT 81.050 110.120 82.710 110.665 ;
430+
RECT 83.810 110.120 85.470 110.665 ;
431+
RECT 86.570 110.120 88.230 110.665 ;
432+
RECT 89.330 110.120 90.990 110.665 ;
433+
RECT 92.090 110.120 93.750 110.665 ;
434+
RECT 94.850 110.120 96.510 110.665 ;
435+
RECT 97.610 110.120 99.270 110.665 ;
436+
RECT 100.370 110.120 102.030 110.665 ;
437+
RECT 103.130 110.120 104.790 110.665 ;
438+
RECT 105.890 110.120 107.550 110.665 ;
439+
RECT 108.650 110.120 110.310 110.665 ;
440+
RECT 111.410 110.120 113.070 110.665 ;
441+
RECT 114.170 110.120 115.830 110.665 ;
442+
RECT 116.930 110.120 118.590 110.665 ;
443+
RECT 119.690 110.120 121.350 110.665 ;
444+
RECT 122.450 110.120 124.110 110.665 ;
445+
RECT 125.210 110.120 126.870 110.665 ;
446+
RECT 127.970 110.120 129.630 110.665 ;
447+
RECT 130.730 110.120 132.390 110.665 ;
448+
RECT 133.490 110.120 135.150 110.665 ;
449+
RECT 136.250 110.120 137.910 110.665 ;
450+
RECT 139.010 110.120 140.670 110.665 ;
451+
RECT 141.770 110.120 143.430 110.665 ;
451452
RECT 30.655 109.440 144.145 110.120 ;
452-
RECT 30.655 103.535 56.750 109.440 ;
453-
RECT 59.150 103.535 60.050 109.440 ;
454-
RECT 62.450 103.535 95.620 109.440 ;
455-
RECT 98.020 103.535 98.920 109.440 ;
456-
RECT 101.320 103.535 134.490 109.440 ;
457-
RECT 136.890 103.535 137.790 109.440 ;
458-
RECT 140.190 103.535 144.145 109.440 ;
453+
RECT 30.655 74.975 56.750 109.440 ;
454+
RECT 59.150 74.975 60.050 109.440 ;
455+
RECT 62.450 74.975 95.620 109.440 ;
456+
RECT 98.020 74.975 98.920 109.440 ;
457+
RECT 101.320 74.975 134.490 109.440 ;
458+
RECT 136.890 74.975 137.790 109.440 ;
459+
RECT 140.190 74.975 144.145 109.440 ;
459460
END
460461
END tt_um_UartMain
461462
END LIBRARY

‎projects/tt_um_UartMain/tt_um_UartMain.oas‎

3.77 KB
Binary file not shown.

0 commit comments

Comments
 (0)