feat: update project tt_um_asgerwenneb from AsgerWenneb/trt10-verilog

Commit: e9ffcbf662c684ba1648f3e016dce9b910df7d67
Workflow: https://github.com/AsgerWenneb/trt10-verilog/actions/runs/13346878618

Author: TinyTapeoutBot

projects/tt_um_asgerwenneb/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt10 0985eb1d",
   "repo": "https://github.com/AsgerWenneb/trt10-verilog",
-  "commit": "26a589dae3eae6555d59a1069996857abc02d4c5",
-  "workflow_url": "https://github.com/AsgerWenneb/trt10-verilog/actions/runs/13345957766",
+  "commit": "e9ffcbf662c684ba1648f3e016dce9b910df7d67",
+  "workflow_url": "https://github.com/AsgerWenneb/trt10-verilog/actions/runs/13346878618",
   "sort_id": 1739633261559,
   "openlane_version": "OpenLane2 2.2.9",
   "pdk_version": "open_pdks 0fe599b2afb6708d281543108caf8310912f54af"

projects/tt_um_asgerwenneb/info.yaml

@@ -8,7 +8,7 @@ project:
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
   top_module:  "tt_um_asgerwenneb"

projects/tt_um_asgerwenneb/stats/metrics.csv

@@ -3,21 +3,21 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,294
-design__instance__area,835.802
+design__instance__count,525
+design__instance__area,1108.56
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.00000961968362389598
-power__switching__total,0.00001715708822302986
-power__leakage__total,1.736365828897135E-9
-power__total,0.000026778508981806226
+power__internal__total,0.00000937501772568794
+power__switching__total,0.000016761252481956035
+power__leakage__total,2.9334343842890576E-9
+power__total,0.000026139203328057192
 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
-timing__hold__ws__corner:nom_tt_025C_1v80,8.146548555216777
-timing__setup__ws__corner:nom_tt_025C_1v80,10.004972244978712
+timing__hold__ws__corner:nom_tt_025C_1v80,8.12726176028752
+timing__setup__ws__corner:nom_tt_025C_1v80,9.927768221841218
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
-timing__hold__ws__corner:nom_ss_100C_1v60,8.500889122134417
-timing__setup__ws__corner:nom_ss_100C_1v60,8.482775610930767
+timing__hold__ws__corner:nom_ss_100C_1v60,8.463347595628786
+timing__setup__ws__corner:nom_ss_100C_1v60,8.327235137138638
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
-timing__hold__ws__corner:nom_ff_n40C_1v95,8.013767654073147
-timing__setup__ws__corner:nom_ff_n40C_1v95,10.607540035476067
+timing__hold__ws__corner:nom_ff_n40C_1v95,8.00147792893218
+timing__setup__ws__corner:nom_ff_n40C_1v95,10.566538165749419
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -67,8 +67,8 @@ design__max_fanout_violation__count,0
 design__max_cap_violation__count,0
 clock__skew__worst_hold,0.0
 clock__skew__worst_setup,0.0
-timing__hold__ws,8.009577228170489
-timing__setup__ws,8.46962524087677
+timing__hold__ws,7.998328448166849
+timing__setup__ws,8.307798240052207
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -79,22 +79,22 @@ timing__hold_r2r_vio__count,0
 timing__setup_vio__count,0
 timing__setup_r2r__ws,inf
 timing__setup_r2r_vio__count,0
-design__die__bbox,0.0 0.0 161.0 111.52
-design__core__bbox,2.76 2.72 158.24 108.8
+design__die__bbox,0.0 0.0 161.0 225.76
+design__core__bbox,2.76 2.72 158.24 223.04
 design__io,45
-design__die__area,17954.7
-design__core__area,16493.3
-design__instance__count__stdcell,294
-design__instance__area__stdcell,835.802
+design__die__area,36347.4
+design__core__area,34255.4
+design__instance__count__stdcell,525
+design__instance__area__stdcell,1108.56
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.0506752
-design__instance__utilization__stdcell,0.0506752
+design__instance__utilization,0.0323618
+design__instance__utilization__stdcell,0.0323618
 design__instance__count__class:multi_input_combinational_cell,53
 flow__warnings__count,1
 flow__errors__count,0
-design__instance__count__class:fill_cell,1443
-design__instance__count__class:tap_cell,225
+design__instance__count__class:fill_cell,3025
+design__instance__count__class:tap_cell,456
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count,0
@@ -103,7 +103,7 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,1108.94
+route__wirelength__estimated,1010.34
 design__violations,0
 design__instance__count__class:timing_repair_buffer,16
 design__instance__count__setup_buffer,0
@@ -114,22 +114,22 @@ route__antenna_violation__count,0
 antenna_diodes_count,0
 route__net,88
 route__net__special,2
-route__drc_errors__iter:1,9
-route__wirelength__iter:1,1013
-route__drc_errors__iter:2,6
-route__wirelength__iter:2,1019
+route__drc_errors__iter:1,19
+route__wirelength__iter:1,941
+route__drc_errors__iter:2,1
+route__wirelength__iter:2,918
 route__drc_errors__iter:3,1
-route__wirelength__iter:3,1018
+route__wirelength__iter:3,922
 route__drc_errors__iter:4,0
-route__wirelength__iter:4,1021
+route__wirelength__iter:4,926
 route__drc_errors,0
-route__wirelength,1021
-route__vias,396
-route__vias__singlecut,396
+route__wirelength,926
+route__vias,409
+route__vias__singlecut,409
 route__vias__multicut,0
 design__disconnected_pin__count,3
 design__critical_disconnected_pin__count,0
-route__wirelength__max,46.7
+route__wirelength__max,42.46
 timing__unannotated_net__count__corner:nom_tt_025C_1v80,19
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
 timing__unannotated_net__count__corner:nom_ss_100C_1v60,19
@@ -141,8 +141,8 @@ design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
-timing__hold__ws__corner:min_tt_025C_1v80,8.140560456141804
-timing__setup__ws__corner:min_tt_025C_1v80,10.014076962216556
+timing__hold__ws__corner:min_tt_025C_1v80,8.122805769029862
+timing__setup__ws__corner:min_tt_025C_1v80,9.939411353074357
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -160,8 +160,8 @@ design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
-timing__hold__ws__corner:min_ss_100C_1v60,8.489994725330261
-timing__setup__ws__corner:min_ss_100C_1v60,8.499093225318992
+timing__hold__ws__corner:min_ss_100C_1v60,8.455373529551196
+timing__setup__ws__corner:min_ss_100C_1v60,8.346326532810034
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -179,8 +179,8 @@ design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
-timing__hold__ws__corner:min_ff_n40C_1v95,8.009577228170489
-timing__setup__ws__corner:min_ff_n40C_1v95,10.613825674330055
+timing__hold__ws__corner:min_ff_n40C_1v95,7.998328448166849
+timing__setup__ws__corner:min_ff_n40C_1v95,10.575595809529688
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -198,8 +198,8 @@ design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
-timing__hold__ws__corner:max_tt_025C_1v80,8.152205363731833
-timing__setup__ws__corner:max_tt_025C_1v80,9.996970645369332
+timing__hold__ws__corner:max_tt_025C_1v80,8.13137669102237
+timing__setup__ws__corner:max_tt_025C_1v80,9.916014956480922
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -217,8 +217,8 @@ design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
-timing__hold__ws__corner:max_ss_100C_1v60,8.510464573948017
-timing__setup__ws__corner:max_ss_100C_1v60,8.46962524087677
+timing__hold__ws__corner:max_ss_100C_1v60,8.470103080880083
+timing__setup__ws__corner:max_ss_100C_1v60,8.307798240052207
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -236,8 +236,8 @@ design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
-timing__hold__ws__corner:max_ff_n40C_1v95,8.01803623967895
-timing__setup__ws__corner:max_ff_n40C_1v95,10.60140183424392
+timing__hold__ws__corner:max_ff_n40C_1v95,8.004644285087961
+timing__setup__ws__corner:max_ff_n40C_1v95,10.55806671974273
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -254,19 +254,19 @@ timing__unannotated_net__count,19
 timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79999
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000119437
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000012029
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,4.87686E-7
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000012029
-design_powergrid__voltage__worst,0.000012029
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000012045
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000112909
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,2.06312E-7
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000112909
+design_powergrid__voltage__worst,0.0000112909
 design_powergrid__voltage__worst__net:VPWR,1.79999
-design_powergrid__drop__worst,0.000012029
-design_powergrid__drop__worst__net:VPWR,0.0000119437
-design_powergrid__voltage__worst__net:VGND,0.000012029
-design_powergrid__drop__worst__net:VGND,0.000012029
+design_powergrid__drop__worst,0.000012045
+design_powergrid__drop__worst__net:VPWR,0.000012045
+design_powergrid__voltage__worst__net:VGND,0.0000112909
+design_powergrid__drop__worst__net:VGND,0.0000112909
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,4.1100000000000001422400066654339045868482571677304804325103759765625E-7
-ir__drop__worst,0.000011899999999999999567381649134834020742346183396875858306884765625
+ir__drop__avg,2.22999999999999998379158409715639077575133342179469764232635498046875E-7
+ir__drop__worst,0.0000120000000000000003040102891649354432956897653639316558837890625
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0