Skip to content

Commit f0cfd02

Browse files
TinyTapeoutBoturish
TinyTapeoutBot
authored and
urish
committed
feat: update project tt_um_urish_simon from urish/tt10-simon-game
Commit: 2a1b9db329e70c1a1238c3e2dc559d441da85549 Workflow: https://github.com/urish/tt10-simon-game/actions/runs/12467975214
1 parent defd6c0 commit f0cfd02

File tree

7 files changed

+5754
-5931
lines changed

7 files changed

+5754
-5931
lines changed

‎projects/tt_um_urish_simon/commit_id.json

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
{
22
"app": "Tiny Tapeout tt10 d89635e1",
33
"repo": "https://github.com/urish/tt10-simon-game",
4-
"commit": "1e0f26fa224d369c76c6349d9298514cad6d727a",
5-
"workflow_url": "https://github.com/urish/tt10-simon-game/actions/runs/12453725870",
4+
"commit": "2a1b9db329e70c1a1238c3e2dc559d441da85549",
5+
"workflow_url": "https://github.com/urish/tt10-simon-game/actions/runs/12467975214",
66
"sort_id": 1734941984438,
77
"openlane_version": "OpenLane2 2.2.9",
88
"pdk_version": "open_pdks 0fe599b2afb6708d281543108caf8310912f54af"

‎projects/tt_um_urish_simon/info.yaml

+1
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ project:
1515

1616
# List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
1717
source_files:
18+
- "clock_divider_stage.v"
1819
- "galois_lfsr.v"
1920
- "inverter.v"
2021
- "project.v"

‎projects/tt_um_urish_simon/stats/metrics.csv

+124-124
Large diffs are not rendered by default.

‎projects/tt_um_urish_simon/stats/synthesis-stats.txt

+122-103
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,22 @@
1-
69. Printing statistics.
1+
70. Printing statistics.
2+
3+
=== clock_divider_stage ===
4+
5+
Number of wires: 4
6+
Number of wire bits: 4
7+
Number of public wires: 3
8+
Number of public wire bits: 3
9+
Number of ports: 3
10+
Number of port bits: 3
11+
Number of memories: 0
12+
Number of memory bits: 0
13+
Number of processes: 0
14+
Number of cells: 2
15+
sky130_fd_sc_hd__dfxtp_2 1
16+
sky130_fd_sc_hd__inv_2 1
17+
18+
Chip area for module '\clock_divider_stage': 25.024000
19+
of which used for sequential elements: 21.270400 (85.00%)
220

321
=== inverter ===
422

@@ -19,157 +37,158 @@
1937

2038
=== tt_um_urish_simon ===
2139

22-
Number of wires: 1190
23-
Number of wire bits: 1225
40+
Number of wires: 1148
41+
Number of wire bits: 1183
2442
Number of public wires: 218
2543
Number of public wire bits: 253
2644
Number of ports: 8
2745
Number of port bits: 43
2846
Number of memories: 0
2947
Number of memory bits: 0
3048
Number of processes: 0
31-
Number of cells: 1206
49+
Number of cells: 1164
50+
clock_divider_stage 13
3251
inverter 13
33-
sky130_fd_sc_hd__a2111o_2 2
52+
sky130_fd_sc_hd__a2111o_2 3
3453
sky130_fd_sc_hd__a211o_2 12
35-
sky130_fd_sc_hd__a211oi_2 2
54+
sky130_fd_sc_hd__a211oi_2 1
3655
sky130_fd_sc_hd__a21bo_2 5
37-
sky130_fd_sc_hd__a21boi_2 1
38-
sky130_fd_sc_hd__a21o_2 25
39-
sky130_fd_sc_hd__a21oi_2 32
40-
sky130_fd_sc_hd__a221o_2 2
56+
sky130_fd_sc_hd__a21boi_2 2
57+
sky130_fd_sc_hd__a21o_2 16
58+
sky130_fd_sc_hd__a21oi_2 26
59+
sky130_fd_sc_hd__a221o_2 3
4160
sky130_fd_sc_hd__a22o_2 18
4261
sky130_fd_sc_hd__a2bb2o_2 8
43-
sky130_fd_sc_hd__a311o_2 5
44-
sky130_fd_sc_hd__a31o_2 21
45-
sky130_fd_sc_hd__a31oi_2 2
46-
sky130_fd_sc_hd__a32o_2 18
47-
sky130_fd_sc_hd__a41o_2 3
48-
sky130_fd_sc_hd__and2_2 96
49-
sky130_fd_sc_hd__and2b_2 12
50-
sky130_fd_sc_hd__and3_2 36
62+
sky130_fd_sc_hd__a311o_2 1
63+
sky130_fd_sc_hd__a31o_2 20
64+
sky130_fd_sc_hd__a31oi_2 6
65+
sky130_fd_sc_hd__a32o_2 12
66+
sky130_fd_sc_hd__a41o_2 4
67+
sky130_fd_sc_hd__and2_2 77
68+
sky130_fd_sc_hd__and2b_2 10
69+
sky130_fd_sc_hd__and3_2 43
5170
sky130_fd_sc_hd__and3b_2 9
52-
sky130_fd_sc_hd__and4_2 14
71+
sky130_fd_sc_hd__and4_2 13
5372
sky130_fd_sc_hd__and4b_2 3
5473
sky130_fd_sc_hd__and4bb_2 2
5574
sky130_fd_sc_hd__buf_2 2
5675
sky130_fd_sc_hd__conb_1 9
57-
sky130_fd_sc_hd__dfxtp_2 208
58-
sky130_fd_sc_hd__inv_2 28
59-
sky130_fd_sc_hd__mux2_1 80
60-
sky130_fd_sc_hd__nand2_2 65
61-
sky130_fd_sc_hd__nand2b_2 5
62-
sky130_fd_sc_hd__nand3_2 6
63-
sky130_fd_sc_hd__nor2_2 67
64-
sky130_fd_sc_hd__nor3_2 3
65-
sky130_fd_sc_hd__nor3b_2 1
66-
sky130_fd_sc_hd__nor4_2 2
76+
sky130_fd_sc_hd__dfxtp_2 195
77+
sky130_fd_sc_hd__inv_2 33
78+
sky130_fd_sc_hd__mux2_1 78
79+
sky130_fd_sc_hd__nand2_2 57
80+
sky130_fd_sc_hd__nand2b_2 7
81+
sky130_fd_sc_hd__nand3_2 5
82+
sky130_fd_sc_hd__nand4_2 1
83+
sky130_fd_sc_hd__nor2_2 64
84+
sky130_fd_sc_hd__nor3_2 4
85+
sky130_fd_sc_hd__nor3b_2 2
86+
sky130_fd_sc_hd__nor4_2 3
6787
sky130_fd_sc_hd__nor4b_2 1
6888
sky130_fd_sc_hd__o2111a_2 2
69-
sky130_fd_sc_hd__o2111ai_2 1
70-
sky130_fd_sc_hd__o211a_2 61
71-
sky130_fd_sc_hd__o211ai_2 3
72-
sky130_fd_sc_hd__o21a_2 18
73-
sky130_fd_sc_hd__o21ai_2 31
74-
sky130_fd_sc_hd__o21ba_2 3
75-
sky130_fd_sc_hd__o21bai_2 1
76-
sky130_fd_sc_hd__o221a_2 14
77-
sky130_fd_sc_hd__o22a_2 3
78-
sky130_fd_sc_hd__o2bb2a_2 2
79-
sky130_fd_sc_hd__o311a_2 3
80-
sky130_fd_sc_hd__o31a_2 8
81-
sky130_fd_sc_hd__o31ai_2 1
82-
sky130_fd_sc_hd__o32a_2 3
83-
sky130_fd_sc_hd__o41a_2 1
84-
sky130_fd_sc_hd__or2_2 102
89+
sky130_fd_sc_hd__o2111ai_2 2
90+
sky130_fd_sc_hd__o211a_2 62
91+
sky130_fd_sc_hd__o211ai_2 2
92+
sky130_fd_sc_hd__o21a_2 23
93+
sky130_fd_sc_hd__o21ai_2 32
94+
sky130_fd_sc_hd__o21ba_2 5
95+
sky130_fd_sc_hd__o221a_2 12
96+
sky130_fd_sc_hd__o22a_2 1
97+
sky130_fd_sc_hd__o2bb2a_2 5
98+
sky130_fd_sc_hd__o311a_2 7
99+
sky130_fd_sc_hd__o31a_2 5
100+
sky130_fd_sc_hd__o31ai_2 5
101+
sky130_fd_sc_hd__o32a_2 1
102+
sky130_fd_sc_hd__or2_2 96
85103
sky130_fd_sc_hd__or3_2 22
86104
sky130_fd_sc_hd__or3b_2 9
87-
sky130_fd_sc_hd__or4_2 33
88-
sky130_fd_sc_hd__or4b_2 9
105+
sky130_fd_sc_hd__or4_2 30
106+
sky130_fd_sc_hd__or4b_2 4
89107
sky130_fd_sc_hd__or4bb_2 2
90-
sky130_fd_sc_hd__xnor2_2 40
91-
sky130_fd_sc_hd__xor2_2 16
108+
sky130_fd_sc_hd__xnor2_2 35
109+
sky130_fd_sc_hd__xor2_2 21
92110

93111
Area for cell type \inverter is unknown!
112+
Area for cell type \clock_divider_stage is unknown!
94113

95-
Chip area for module '\tt_um_urish_simon': 13135.097600
96-
of which used for sequential elements: 4424.243200 (33.68%)
114+
Chip area for module '\tt_um_urish_simon': 12535.772800
115+
of which used for sequential elements: 4147.728000 (33.09%)
97116

98117
=== design hierarchy ===
99118

100119
tt_um_urish_simon 1
120+
clock_divider_stage 13
101121
inverter 13
102122

103-
Number of wires: 1216
104-
Number of wire bits: 1251
105-
Number of public wires: 244
106-
Number of public wire bits: 279
107-
Number of ports: 34
108-
Number of port bits: 69
123+
Number of wires: 1226
124+
Number of wire bits: 1261
125+
Number of public wires: 283
126+
Number of public wire bits: 318
127+
Number of ports: 73
128+
Number of port bits: 108
109129
Number of memories: 0
110130
Number of memory bits: 0
111131
Number of processes: 0
112-
Number of cells: 1206
113-
sky130_fd_sc_hd__a2111o_2 2
132+
Number of cells: 1177
133+
sky130_fd_sc_hd__a2111o_2 3
114134
sky130_fd_sc_hd__a211o_2 12
115-
sky130_fd_sc_hd__a211oi_2 2
135+
sky130_fd_sc_hd__a211oi_2 1
116136
sky130_fd_sc_hd__a21bo_2 5
117-
sky130_fd_sc_hd__a21boi_2 1
118-
sky130_fd_sc_hd__a21o_2 25
119-
sky130_fd_sc_hd__a21oi_2 32
120-
sky130_fd_sc_hd__a221o_2 2
137+
sky130_fd_sc_hd__a21boi_2 2
138+
sky130_fd_sc_hd__a21o_2 16
139+
sky130_fd_sc_hd__a21oi_2 26
140+
sky130_fd_sc_hd__a221o_2 3
121141
sky130_fd_sc_hd__a22o_2 18
122142
sky130_fd_sc_hd__a2bb2o_2 8
123-
sky130_fd_sc_hd__a311o_2 5
124-
sky130_fd_sc_hd__a31o_2 21
125-
sky130_fd_sc_hd__a31oi_2 2
126-
sky130_fd_sc_hd__a32o_2 18
127-
sky130_fd_sc_hd__a41o_2 3
128-
sky130_fd_sc_hd__and2_2 96
129-
sky130_fd_sc_hd__and2b_2 12
130-
sky130_fd_sc_hd__and3_2 36
143+
sky130_fd_sc_hd__a311o_2 1
144+
sky130_fd_sc_hd__a31o_2 20
145+
sky130_fd_sc_hd__a31oi_2 6
146+
sky130_fd_sc_hd__a32o_2 12
147+
sky130_fd_sc_hd__a41o_2 4
148+
sky130_fd_sc_hd__and2_2 77
149+
sky130_fd_sc_hd__and2b_2 10
150+
sky130_fd_sc_hd__and3_2 43
131151
sky130_fd_sc_hd__and3b_2 9
132-
sky130_fd_sc_hd__and4_2 14
152+
sky130_fd_sc_hd__and4_2 13
133153
sky130_fd_sc_hd__and4b_2 3
134154
sky130_fd_sc_hd__and4bb_2 2
135155
sky130_fd_sc_hd__buf_2 2
136156
sky130_fd_sc_hd__conb_1 9
137157
sky130_fd_sc_hd__dfxtp_2 208
138-
sky130_fd_sc_hd__inv_2 41
139-
sky130_fd_sc_hd__mux2_1 80
140-
sky130_fd_sc_hd__nand2_2 65
141-
sky130_fd_sc_hd__nand2b_2 5
142-
sky130_fd_sc_hd__nand3_2 6
143-
sky130_fd_sc_hd__nor2_2 67
144-
sky130_fd_sc_hd__nor3_2 3
145-
sky130_fd_sc_hd__nor3b_2 1
146-
sky130_fd_sc_hd__nor4_2 2
158+
sky130_fd_sc_hd__inv_2 59
159+
sky130_fd_sc_hd__mux2_1 78
160+
sky130_fd_sc_hd__nand2_2 57
161+
sky130_fd_sc_hd__nand2b_2 7
162+
sky130_fd_sc_hd__nand3_2 5
163+
sky130_fd_sc_hd__nand4_2 1
164+
sky130_fd_sc_hd__nor2_2 64
165+
sky130_fd_sc_hd__nor3_2 4
166+
sky130_fd_sc_hd__nor3b_2 2
167+
sky130_fd_sc_hd__nor4_2 3
147168
sky130_fd_sc_hd__nor4b_2 1
148169
sky130_fd_sc_hd__o2111a_2 2
149-
sky130_fd_sc_hd__o2111ai_2 1
150-
sky130_fd_sc_hd__o211a_2 61
151-
sky130_fd_sc_hd__o211ai_2 3
152-
sky130_fd_sc_hd__o21a_2 18
153-
sky130_fd_sc_hd__o21ai_2 31
154-
sky130_fd_sc_hd__o21ba_2 3
155-
sky130_fd_sc_hd__o21bai_2 1
156-
sky130_fd_sc_hd__o221a_2 14
157-
sky130_fd_sc_hd__o22a_2 3
158-
sky130_fd_sc_hd__o2bb2a_2 2
159-
sky130_fd_sc_hd__o311a_2 3
160-
sky130_fd_sc_hd__o31a_2 8
161-
sky130_fd_sc_hd__o31ai_2 1
162-
sky130_fd_sc_hd__o32a_2 3
163-
sky130_fd_sc_hd__o41a_2 1
164-
sky130_fd_sc_hd__or2_2 102
170+
sky130_fd_sc_hd__o2111ai_2 2
171+
sky130_fd_sc_hd__o211a_2 62
172+
sky130_fd_sc_hd__o211ai_2 2
173+
sky130_fd_sc_hd__o21a_2 23
174+
sky130_fd_sc_hd__o21ai_2 32
175+
sky130_fd_sc_hd__o21ba_2 5
176+
sky130_fd_sc_hd__o221a_2 12
177+
sky130_fd_sc_hd__o22a_2 1
178+
sky130_fd_sc_hd__o2bb2a_2 5
179+
sky130_fd_sc_hd__o311a_2 7
180+
sky130_fd_sc_hd__o31a_2 5
181+
sky130_fd_sc_hd__o31ai_2 5
182+
sky130_fd_sc_hd__o32a_2 1
183+
sky130_fd_sc_hd__or2_2 96
165184
sky130_fd_sc_hd__or3_2 22
166185
sky130_fd_sc_hd__or3b_2 9
167-
sky130_fd_sc_hd__or4_2 33
168-
sky130_fd_sc_hd__or4b_2 9
186+
sky130_fd_sc_hd__or4_2 30
187+
sky130_fd_sc_hd__or4b_2 4
169188
sky130_fd_sc_hd__or4bb_2 2
170-
sky130_fd_sc_hd__xnor2_2 40
171-
sky130_fd_sc_hd__xor2_2 16
189+
sky130_fd_sc_hd__xnor2_2 35
190+
sky130_fd_sc_hd__xor2_2 21
172191

173-
Chip area for top module '\tt_um_urish_simon': 13183.894400
192+
Chip area for top module '\tt_um_urish_simon': 12909.881600
174193
of which used for sequential elements: 0.000000 (0.00%)
175194

‎projects/tt_um_urish_simon/tt_um_urish_simon.gds

62.9 KB
Binary file not shown.

‎projects/tt_um_urish_simon/tt_um_urish_simon.lef

+12-12
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ MACRO tt_um_urish_simon
112112
PIN ui_in[4]
113113
DIRECTION INPUT ;
114114
USE SIGNAL ;
115-
ANTENNAGATEAREA 0.126000 ;
115+
ANTENNAGATEAREA 0.196500 ;
116116
PORT
117117
LAYER met4 ;
118118
RECT 127.270 110.520 127.570 111.520 ;
@@ -412,7 +412,7 @@ MACRO tt_um_urish_simon
412412
PIN uo_out[7]
413413
DIRECTION OUTPUT ;
414414
USE SIGNAL ;
415-
ANTENNADIFFAREA 0.795200 ;
415+
ANTENNADIFFAREA 0.445500 ;
416416
PORT
417417
LAYER met4 ;
418418
RECT 74.830 110.520 75.130 111.520 ;
@@ -424,11 +424,11 @@ MACRO tt_um_urish_simon
424424
LAYER li1 ;
425425
RECT 2.760 2.635 158.240 108.885 ;
426426
LAYER met1 ;
427-
RECT 2.760 2.480 158.540 109.440 ;
427+
RECT 2.760 2.480 158.240 109.440 ;
428428
LAYER met2 ;
429-
RECT 4.240 2.535 156.760 110.005 ;
429+
RECT 4.240 2.535 156.770 110.005 ;
430430
LAYER met3 ;
431-
RECT 9.725 2.555 154.495 109.985 ;
431+
RECT 6.965 2.555 156.795 109.985 ;
432432
LAYER met4 ;
433433
RECT 31.370 110.120 33.030 110.520 ;
434434
RECT 34.130 110.120 35.790 110.520 ;
@@ -472,13 +472,13 @@ MACRO tt_um_urish_simon
472472
RECT 139.010 110.120 140.670 110.520 ;
473473
RECT 141.770 110.120 143.430 110.520 ;
474474
RECT 30.655 109.440 144.145 110.120 ;
475-
RECT 30.655 19.895 56.750 109.440 ;
476-
RECT 59.150 19.895 60.050 109.440 ;
477-
RECT 62.450 19.895 95.620 109.440 ;
478-
RECT 98.020 19.895 98.920 109.440 ;
479-
RECT 101.320 19.895 134.490 109.440 ;
480-
RECT 136.890 19.895 137.790 109.440 ;
481-
RECT 140.190 19.895 144.145 109.440 ;
475+
RECT 30.655 45.055 56.750 109.440 ;
476+
RECT 59.150 45.055 60.050 109.440 ;
477+
RECT 62.450 45.055 95.620 109.440 ;
478+
RECT 98.020 45.055 98.920 109.440 ;
479+
RECT 101.320 45.055 134.490 109.440 ;
480+
RECT 136.890 45.055 137.790 109.440 ;
481+
RECT 140.190 45.055 144.145 109.440 ;
482482
END
483483
END tt_um_urish_simon
484484
END LIBRARY

0 commit comments

Comments
 (0)