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author
htfab
committed
feat: make padframe and mux similar to TT06+
1 parent 4fcc672 commit 83c3e49

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9 files changed

+175
-87
lines changed

9 files changed

+175
-87
lines changed

‎designs/ihp-sg13g2/tt-chip/config.mk

+1
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@ export PROJECTS_HOME = $(DESIGN_HOME)/../projects
66
export SEAL_GDS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/macros/sealring/gds/sealring.gds
77

88
export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/tt_top.v \
9+
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/counter.v \
910
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/basic_mux.v \
1011
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/wrappers/p00_wrapper.v \
1112
$(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/wrappers/p01_wrapper.v \

‎designs/ihp-sg13g2/tt-chip/constraint.sdc

+5-1
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,13 @@ set clk_io_pct 0.2
66
set clk_port [get_ports $clk_port_name]
77

88
set clk_input_ports [get_ports {
9-
addr_PAD
9+
ctrl_sel_rst_n_PAD
10+
ctrl_sel_inc_PAD
11+
ctrl_ena_PAD
1012
clk_PAD
1113
rst_n_PAD
1214
ui_in_PAD
15+
loopback_in_PAD
1316
}]
1417

1518
set clk_inout_ports [get_ports {
@@ -18,6 +21,7 @@ set clk_inout_ports [get_ports {
1821

1922
set clk_output_ports [get_ports {
2023
uo_out_PAD
24+
loopback_out_PAD
2125
}]
2226

2327
create_clock -name $clk_name -period $clk_period $clk_port

‎designs/ihp-sg13g2/tt-chip/pad.tcl

+50-50
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ set IO_WIDTH 80
55
set BONDPAD_SIZE 70
66
set SEALRING_OFFSET 70
77
set MAX_NUM_PADS_HORIZONTAL 12
8-
set MAX_NUM_PADS_VERTICAL 11
8+
set MAX_NUM_PADS_VERTICAL 12
99

1010
proc calc_horizontal_pad_location {index} {
1111
global IO_LENGTH
@@ -49,57 +49,57 @@ make_io_sites \
4949
-offset $IO_OFFSET
5050

5151
# Place Pads
52-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 0] {sg13g2_IOPadIOVdd_1} -master sg13g2_IOPadIOVdd
53-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 1] {sg13g2_IOPadIOVss_1} -master sg13g2_IOPadIOVss
54-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 2] {sg13g2_IOPadVss_1} -master sg13g2_IOPadVss
55-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 3] {sg13g2_IOPadVdd_1} -master sg13g2_IOPadVdd
56-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 4] {sg13g2_ui_in_0}
57-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 5] {sg13g2_ui_in_1}
58-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 6] {sg13g2_ui_in_2}
59-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 7] {sg13g2_ui_in_3}
60-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 8] {sg13g2_ui_in_4}
61-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 9] {sg13g2_ui_in_5}
62-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 10] {sg13g2_ui_in_6}
63-
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 11] {sg13g2_ui_in_7}
64-
65-
66-
place_pad -row IO_EAST -location [calc_vertical_pad_location 0] {sg13g2_IOPadIOVdd_2} -master sg13g2_IOPadIOVdd
67-
place_pad -row IO_EAST -location [calc_vertical_pad_location 1] {sg13g2_IOPadIOVss_2} -master sg13g2_IOPadIOVss
68-
place_pad -row IO_EAST -location [calc_vertical_pad_location 2] {sg13g2_IOPadVss_2} -master sg13g2_IOPadVss
69-
place_pad -row IO_EAST -location [calc_vertical_pad_location 3] {sg13g2_IOPadVdd_2} -master sg13g2_IOPadVdd
70-
place_pad -row IO_EAST -location [calc_vertical_pad_location 4] {sg13g2_addr_0}
71-
place_pad -row IO_EAST -location [calc_vertical_pad_location 5] {sg13g2_addr_1}
72-
place_pad -row IO_EAST -location [calc_vertical_pad_location 6] {sg13g2_addr_2}
73-
place_pad -row IO_EAST -location [calc_vertical_pad_location 7] {sg13g2_addr_3}
74-
place_pad -row IO_EAST -location [calc_vertical_pad_location 8] {sg13g2_addr_4}
75-
place_pad -row IO_EAST -location [calc_vertical_pad_location 9] {sg13g2_clk}
76-
place_pad -row IO_EAST -location [calc_vertical_pad_location 10] {sg13g2_rst_n}
77-
78-
79-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 0] {sg13g2_IOPadIOVdd_3} -master sg13g2_IOPadIOVdd
80-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 1] {sg13g2_IOPadIOVss_3} -master sg13g2_IOPadIOVss
81-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 2] {sg13g2_uio_0}
82-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 3] {sg13g2_uio_1}
83-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 4] {sg13g2_uio_2}
52+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 0] {sg13g2_unused}
53+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 1] {sg13g2_IOPadIOVss_3} -master sg13g2_IOPadIOVss
54+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 2] {sg13g2_ctrl_ena}
55+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 3] {sg13g2_IOPadVss_1} -master sg13g2_IOPadVss
56+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 4] {sg13g2_ctrl_sel_inc}
57+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 5] {sg13g2_ctrl_sel_rst_n}
58+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 6] {sg13g2_IOPadIOVss_1} -master sg13g2_IOPadIOVss
59+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 7] {sg13g2_IOPadIOVdd_3} -master sg13g2_IOPadIOVdd
60+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 8] {sg13g2_ui_in_0}
61+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 9] {sg13g2_ui_in_1}
62+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 10] {sg13g2_ui_in_2}
63+
place_pad -row IO_SOUTH -location [calc_horizontal_pad_location 11] {sg13g2_ui_in_3}
64+
65+
place_pad -row IO_EAST -location [calc_vertical_pad_location 0] {sg13g2_ui_in_4}
66+
place_pad -row IO_EAST -location [calc_vertical_pad_location 1] {sg13g2_ui_in_5}
67+
place_pad -row IO_EAST -location [calc_vertical_pad_location 2] {sg13g2_ui_in_6}
68+
place_pad -row IO_EAST -location [calc_vertical_pad_location 3] {sg13g2_IOPadIOVss_4} -master sg13g2_IOPadIOVss
69+
place_pad -row IO_EAST -location [calc_vertical_pad_location 4] {sg13g2_IOPadVss_2} -master sg13g2_IOPadVss
70+
place_pad -row IO_EAST -location [calc_vertical_pad_location 5] {sg13g2_IOPadIOVdd_4} -master sg13g2_IOPadIOVdd
71+
place_pad -row IO_EAST -location [calc_vertical_pad_location 6] {sg13g2_loopback_in}
72+
place_pad -row IO_EAST -location [calc_vertical_pad_location 7] {sg13g2_loopback_out}
73+
place_pad -row IO_EAST -location [calc_vertical_pad_location 8] {sg13g2_IOPadIOVdd_5} -master sg13g2_IOPadIOVdd
74+
place_pad -row IO_EAST -location [calc_vertical_pad_location 9] {sg13g2_ui_in_7}
75+
place_pad -row IO_EAST -location [calc_vertical_pad_location 10] {sg13g2_IOPadVdd_2} -master sg13g2_IOPadVdd
76+
place_pad -row IO_EAST -location [calc_vertical_pad_location 11] {sg13g2_clk}
77+
78+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 0] {sg13g2_uo_out_0}
79+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 1] {sg13g2_uio_7}
80+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 2] {sg13g2_uio_6}
81+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 3] {sg13g2_uio_5}
82+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 4] {sg13g2_uio_4}
8483
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 5] {sg13g2_uio_3}
85-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 6] {sg13g2_uio_4}
86-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 7] {sg13g2_uio_5}
87-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 8] {sg13g2_uio_6}
88-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 9] {sg13g2_uio_7}
89-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 10] {sg13g2_IOPadIOVss_4} -master sg13g2_IOPadIOVss
90-
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 11] {sg13g2_IOPadIOVdd_4} -master sg13g2_IOPadIOVdd
91-
92-
place_pad -row IO_WEST -location [calc_vertical_pad_location 0] {sg13g2_IOPadIOVdd_5} -master sg13g2_IOPadIOVdd
93-
place_pad -row IO_WEST -location [calc_vertical_pad_location 1] {sg13g2_IOPadIOVss_5} -master sg13g2_IOPadIOVss
84+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 6] {sg13g2_IOPadIOVss_2} -master sg13g2_IOPadIOVss
85+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 7] {sg13g2_uio_2}
86+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 8] {sg13g2_uio_1}
87+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 9] {sg13g2_uio_0}
88+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 10] {sg13g2_IOPadIOVss_5} -master sg13g2_IOPadIOVss
89+
place_pad -row IO_NORTH -location [calc_horizontal_pad_location 11] {sg13g2_rst_n}
90+
91+
place_pad -row IO_WEST -location [calc_vertical_pad_location 0] {sg13g2_IOPadVdd_1} -master sg13g2_IOPadVdd
92+
place_pad -row IO_WEST -location [calc_vertical_pad_location 1] {sg13g2_IOPadIOVdd_1} -master sg13g2_IOPadIOVdd
9493
place_pad -row IO_WEST -location [calc_vertical_pad_location 2] {sg13g2_IOPadVss_3} -master sg13g2_IOPadVss
95-
place_pad -row IO_WEST -location [calc_vertical_pad_location 3] {sg13g2_uo_out_0}
96-
place_pad -row IO_WEST -location [calc_vertical_pad_location 4] {sg13g2_uo_out_1}
97-
place_pad -row IO_WEST -location [calc_vertical_pad_location 5] {sg13g2_uo_out_2}
98-
place_pad -row IO_WEST -location [calc_vertical_pad_location 6] {sg13g2_uo_out_3}
99-
place_pad -row IO_WEST -location [calc_vertical_pad_location 7] {sg13g2_uo_out_4}
100-
place_pad -row IO_WEST -location [calc_vertical_pad_location 8] {sg13g2_uo_out_5}
101-
place_pad -row IO_WEST -location [calc_vertical_pad_location 9] {sg13g2_uo_out_6}
102-
place_pad -row IO_WEST -location [calc_vertical_pad_location 10] {sg13g2_uo_out_7}
94+
place_pad -row IO_WEST -location [calc_vertical_pad_location 3] {sg13g2_uo_out_7}
95+
place_pad -row IO_WEST -location [calc_vertical_pad_location 4] {sg13g2_uo_out_6}
96+
place_pad -row IO_WEST -location [calc_vertical_pad_location 5] {sg13g2_uo_out_5}
97+
place_pad -row IO_WEST -location [calc_vertical_pad_location 6] {sg13g2_uo_out_4}
98+
place_pad -row IO_WEST -location [calc_vertical_pad_location 7] {sg13g2_uo_out_3}
99+
place_pad -row IO_WEST -location [calc_vertical_pad_location 8] {sg13g2_uo_out_2}
100+
place_pad -row IO_WEST -location [calc_vertical_pad_location 9] {sg13g2_uo_out_1}
101+
place_pad -row IO_WEST -location [calc_vertical_pad_location 10] {sg13g2_IOPadIOVdd_2} -master sg13g2_IOPadIOVdd
102+
place_pad -row IO_WEST -location [calc_vertical_pad_location 11] {sg13g2_IOPadVdd_3} -master sg13g2_IOPadVdd
103103

104104

105105
# Place Corner Cells and Filler

‎designs/src/tt-chip/basic_mux.v

+16-11
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,13 @@
11
`default_nettype none
22

33
module basic_mux (
4+
input wire ena,
45
input wire [ 4:0] addr,
56
input wire [17:0] iw,
67
output reg [23:0] ow
78
);
89

9-
wire p00_selected = (addr == 5'd00);
10+
wire p00_selected = (addr == 5'd00) & ena;
1011
wire [17:0] p00_iw = p00_selected ? iw : 18'b0;
1112
wire [23:0] p00_ow;
1213
p00_wrapper p00_I (
@@ -15,7 +16,7 @@ module basic_mux (
1516
.ow (p00_ow)
1617
);
1718

18-
wire p01_selected = (addr == 5'd01);
19+
wire p01_selected = (addr == 5'd01) & ena;
1920
wire [17:0] p01_iw = p01_selected ? iw : 18'b0;
2021
wire [23:0] p01_ow;
2122
p01_wrapper p01_I (
@@ -26,7 +27,7 @@ module basic_mux (
2627

2728
`ifndef RTL_TESTBENCH
2829

29-
wire p02_selected = (addr == 5'd02);
30+
wire p02_selected = (addr == 5'd02) & ena;
3031
wire [17:0] p02_iw = p02_selected ? iw : 18'b0;
3132
wire [23:0] p02_ow;
3233
p02_wrapper p02_I (
@@ -35,7 +36,7 @@ module basic_mux (
3536
.ow (p02_ow)
3637
);
3738

38-
wire p03_selected = (addr == 5'd03);
39+
wire p03_selected = (addr == 5'd03) & ena;
3940
wire [17:0] p03_iw = p03_selected ? iw : 18'b0;
4041
wire [23:0] p03_ow;
4142
p03_wrapper p03_I (
@@ -47,15 +48,19 @@ module basic_mux (
4748
`endif // RTL_TESTBENCH
4849

4950
always_comb begin
50-
case (addr)
51-
5'd00: ow = p00_ow;
52-
5'd01: ow = p01_ow;
51+
if (ena) begin
52+
case (addr)
53+
5'd00: ow = p00_ow;
54+
5'd01: ow = p01_ow;
5355
`ifndef RTL_TESTBENCH
54-
5'd02: ow = p02_ow;
55-
5'd03: ow = p03_ow;
56+
5'd02: ow = p02_ow;
57+
5'd03: ow = p03_ow;
5658
`endif // RTL_TESTBENCH
57-
default: ow = 24'b0;
58-
endcase
59+
default: ow = 24'b0;
60+
endcase
61+
end else begin
62+
ow = 24'b0;
63+
end
5964
end
6065

6166
endmodule

‎designs/src/tt-chip/counter.v

+17
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
`default_nettype none
2+
3+
module counter (
4+
input wire ctrl_sel_rst_n,
5+
input wire ctrl_sel_inc,
6+
output reg [4:0] addr
7+
);
8+
9+
always @(posedge ctrl_sel_inc or negedge ctrl_sel_rst_n) begin
10+
if (~ctrl_sel_rst_n) begin
11+
addr <= 5'b0;
12+
end else begin
13+
addr <= addr + 5'b1;
14+
end
15+
end
16+
17+
endmodule

‎designs/src/tt-chip/tt_top.v

+46-20
Original file line numberDiff line numberDiff line change
@@ -1,42 +1,43 @@
11
`default_nettype none
22

33
module tt_top (
4-
inout [4:0] addr_PAD,
4+
inout ctrl_sel_rst_n_PAD,
5+
inout ctrl_sel_inc_PAD,
6+
inout ctrl_ena_PAD,
57
inout [7:0] ui_in_PAD,
68
inout [7:0] uo_out_PAD,
79
inout [7:0] uio_PAD,
810
inout clk_PAD,
9-
inout rst_n_PAD
11+
inout rst_n_PAD,
12+
inout loopback_in_PAD,
13+
inout loopback_out_PAD,
14+
inout unused_PAD
1015
);
1116

12-
wire [4:0] addr;
17+
wire ctrl_sel_rst_n;
18+
wire ctrl_sel_inc;
19+
wire ctrl_ena;
1320
wire [7:0] ui_in;
1421
wire [7:0] uo_out;
1522
wire [7:0] uio_in;
1623
wire [7:0] uio_out;
1724
wire [7:0] uio_oe;
1825
wire clk;
1926
wire rst_n;
27+
wire loopback;
28+
wire _unused;
2029

21-
sg13g2_IOPadIn sg13g2_addr_0 (
22-
.p2c(addr[0]),
23-
.pad({addr_PAD[0]})
24-
);
25-
sg13g2_IOPadIn sg13g2_addr_1 (
26-
.p2c(addr[1]),
27-
.pad({addr_PAD[1]})
30+
sg13g2_IOPadIn sg13g2_ctrl_sel_rst_n (
31+
.p2c(ctrl_sel_rst_n),
32+
.pad({ctrl_sel_rst_n_PAD})
2833
);
29-
sg13g2_IOPadIn sg13g2_addr_2 (
30-
.p2c(addr[2]),
31-
.pad({addr_PAD[2]})
34+
sg13g2_IOPadIn sg13g2_ctrl_sel_inc (
35+
.p2c(ctrl_sel_inc),
36+
.pad({ctrl_sel_inc_PAD})
3237
);
33-
sg13g2_IOPadIn sg13g2_addr_3 (
34-
.p2c(addr[3]),
35-
.pad({addr_PAD[3]})
36-
);
37-
sg13g2_IOPadIn sg13g2_addr_4 (
38-
.p2c(addr[4]),
39-
.pad({addr_PAD[4]})
38+
sg13g2_IOPadIn sg13g2_ctrl_ena (
39+
.p2c(ctrl_ena),
40+
.pad({ctrl_ena_PAD})
4041
);
4142
sg13g2_IOPadIn sg13g2_ui_in_0 (
4243
.p2c(ui_in[0]),
@@ -80,6 +81,17 @@ module tt_top (
8081
.pad({rst_n_PAD})
8182
);
8283

84+
sg13g2_IOPadIn sg13g2_loopback_in (
85+
.p2c(loopback),
86+
.pad({loopback_in_PAD})
87+
);
88+
89+
(* keep *)
90+
sg13g2_IOPadIn sg13g2_unused (
91+
.p2c(_unused),
92+
.pad({unused_PAD})
93+
);
94+
8395
sg13g2_IOPadInOut4mA sg13g2_uio_0 (
8496
.c2p (uio_out[0]),
8597
.c2p_en(uio_oe[0]),
@@ -162,13 +174,27 @@ module tt_top (
162174
.pad({uo_out_PAD[7]})
163175
);
164176

177+
sg13g2_IOPadOut4mA sg13g2_loopback_out (
178+
.c2p(loopback),
179+
.pad({loopback_out_PAD})
180+
);
181+
182+
wire [4:0] addr;
183+
184+
counter counter_I (
185+
.ctrl_sel_rst_n(ctrl_sel_rst_n),
186+
.ctrl_sel_inc (ctrl_sel_inc),
187+
.addr (addr)
188+
);
189+
165190
wire [17:0] iw;
166191
wire [23:0] ow;
167192

168193
assign iw = {uio_in, ui_in, rst_n, clk};
169194
assign {uio_oe, uio_out, uo_out} = ow;
170195

171196
basic_mux mux_I (
197+
.ena (ctrl_ena),
172198
.addr(addr),
173199
.iw (iw),
174200
.ow (ow)

‎test/includes.txt

+1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
-v $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/tt_top.v
2+
-v $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/counter.v
23
-v $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/basic_mux.v
34
-v $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/wrappers/p00_wrapper.v
45
-v $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/wrappers/p01_wrapper.v

‎test/test_mux.py

+23-2
Original file line numberDiff line numberDiff line change
@@ -1,15 +1,27 @@
11
import cocotb
22
from cocotb.types import LogicArray
33
from cocotb.clock import Clock
4-
from cocotb.triggers import ClockCycles
4+
from cocotb.triggers import ClockCycles, Timer
55
import re
66
import os
77
import binascii
88

99

1010
async def enable_design(dut, mux_addr):
1111
dut._log.info(f"enabling design at mux address {mux_addr}")
12-
dut.addr.value = mux_addr
12+
dut.ctrl_ena.value = 0
13+
dut.ctrl_sel_rst_n.value = 0
14+
dut.ctrl_sel_inc.value = 0
15+
await Timer(100, units="ns")
16+
dut.ctrl_sel_rst_n.value = 1
17+
await Timer(100, units="ns")
18+
for i in range(mux_addr):
19+
dut.ctrl_sel_inc.value = 1
20+
await Timer(100, units="ns")
21+
dut.ctrl_sel_inc.value = 0
22+
await Timer(100, units="ns")
23+
dut.ctrl_ena.value = 1
24+
await Timer(100, units="ns")
1325

1426

1527
@cocotb.test()
@@ -93,3 +105,12 @@ async def test_rom(dut):
93105

94106
crc32 = int.from_bytes(buf[252:256], "little")
95107
assert crc32 == binascii.crc32(buf[0:252])
108+
109+
@cocotb.test()
110+
async def test_loopback(dut):
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for c in "loopback test":
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for i in range(8):
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bit = (ord(c) >> i) & 1
114+
dut.loopback_in.value = bit
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await Timer(100, units="ns")
116+
assert dut.loopback_out.value == bit

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