TT DBv3 (ETR) SDK, tested with FPGA and TT08 breakout

Author: psychogenic

src/ttboard/boot/demoboard_detect.py

@@ -139,20 +139,49 @@ def probe_tt04mux(cls):
 
     @classmethod
     def probe_rp2350(cls):
-        try: 
-            _p = Pin(37, Pin.IN)
-        except ValueError:
+        if not platform.IsRP2350:
             return False 
+        
+        # already determined RP2350, so that's good
         cls.PCB = DemoboardVersion.TTDBv3
-        cls.CarrierPresent = True
-        cls.CarrierVersion = DemoboardCarrier.TT_CARRIER # TODO: FIXME just assuming carrier here
-        return True
+        
+        # check for FPGA board
+        fpga_detect_pin = GPIOMapTTDBv3.get_raw_pin(GPIOMapTTDBv3.MNG07, Pin.IN)
+        
+        # mng 7 pulled high?
+        if fpga_detect_pin():
+            cls.CarrierPresent = True
+            cls.CarrierVersion = DemoboardCarrier.FPGA
+            return True
+            
+        
+        # check for standard carrier
+        cena_pin = GPIOMapTT06.get_raw_pin(GPIOMapTTDBv3.ctrl_enable(), Pin.IN)
+        crst_pin = GPIOMapTT06.get_raw_pin(GPIOMapTTDBv3.ctrl_reset(), Pin.IN)
+        
+        crst = crst_pin()
+        cena = cena_pin()
+        
+        if (not crst) and (not cena):
+            log.debug("ctrl mux lines pulled to indicate TT carrier present on RP2350 board")
+            log.info("TTDBv3 demoboard with carrier present")
+            cls.CarrierPresent = True
+            cls.CarrierVersion = DemoboardCarrier.TT_CARRIER
+            return True
+        
+        
+        cls.CarrierVersion = DemoboardCarrier.UNKNOWN
+        return False 
+    
 
     @classmethod 
     def rp_all_inputs(cls):
         log.debug("Setting all RP GPIO to INPUTS")
         pins = []
-        for i in range(29):
+        num_io = 30
+        if platform.IsRP2350:
+            num_io = 41
+        for i in range(num_io):
             pins.append(platform.pin_as_input(i, Pin.PULL_DOWN))
 
         return pins
@@ -186,7 +215,7 @@ def _configure_gpiomap(cls):
             DemoboardVersion.TT06: GPIOMapTT06,
             DemoboardVersion.TTDBv3: GPIOMapTTDBv3,
 
-            }
+        }
         if cls.PCB in mapToUse:
             log.debug(f'Setting GPIOMap to {mapToUse[cls.PCB]}')
             ttboard.pins.gpio_map.GPIOMap = mapToUse[cls.PCB]

src/ttboard/fpga/fabricfoxv2.py

@@ -0,0 +1,294 @@
+'''
+
+FPGA breakout bitstream configurator.
+
+Both PIO and SPI bit bang work to program Lattice FPGAs over the 
+control and mux lines, as defined in the fabricfox FPGA breakout
+project
+
+@author: Pat Deegan
+@copyright: Copyright (C) 2025 Pat Deegan, https://psychogenic.com
+'''
+
+import rp2
+from machine import Pin
+from rp2 import PIO, StateMachine, asm_pio
+import utime
+from ttboard.pins.gpio_map import GPIOMap
+from ttboard.demoboard import DemoBoard
+DoDummyClocks = True
+def pin_indices():
+    '''
+        returns map of pin ID (GPIO #)
+    '''
+    return {
+            'sck': GPIOMap.MNG03, # mng03,
+            'mosi': GPIOMap.MNG00, # mng 00,
+            'ss': GPIOMap.MNG02, # mng02,
+            'reset': GPIOMap.ctrl_reset()
+        }
+
+def pin_objects(tt):
+    '''
+        returns map of pin objects
+    '''
+    # tt.pins.mng00.init(Pin.OUT)
+    # tt.pins.mng02.init(Pin.OUT)
+    # tt.pins.mng03.init(Pin.OUT)
+    return {
+            'sck': tt.pins.mng03,
+            'mosi': tt.pins.mng00,
+            'ss':  tt.pins.mng02,
+            'reset':tt.pins.ncrst
+        }
+    
+
+
+# Simple PIO to do writes over SPI
+
+# PIO program for SPI write-only (8 bits, SCK on Pin 1, MOSI on Pin 2)
+@rp2.asm_pio(
+    sideset_init=(rp2.PIO.OUT_LOW),  # SCK idle low (CPOL=0)
+    out_init=(rp2.PIO.OUT_LOW),      # MOSI idle low
+    out_shiftdir=rp2.PIO.SHIFT_LEFT,  # 
+    autopull=True,                   # Automatically pull 8 bits from FIFO
+    pull_thresh=8,                   # Pull 8 bits at a time
+    fifo_join=rp2.PIO.JOIN_TX        # Optimize for TX FIFO
+)
+def spi_write():
+    wrap_target()
+    set(x, 7) .side(0)               # Initialize loop counter to 7 (for 8 bits), SCK low
+    label("bitloop")
+    out(pins, 1) .side(0) [1]        # Output 1 bit to MOSI, SCK low, delay 1 cycle
+    nop() .side(1) [1]               # SCK high, delay 1 cycle (data sampled here)
+    jmp(x_dec, "bitloop") .side(0)   # Decrement X, loop if not zero, SCK low
+    wrap()
+
+
+
+
+def fpga_reset(ss, reset):
+    # xtra
+    reset.low()
+    ss.low()
+    utime.sleep_us(15000)  # Small delay to ensure reset
+    reset.high()
+    utime.sleep_us(15000)  # delay to ensure slave ready, minimum 1200us
+    
+
+
+def spi_transferPIO(filepath: str, freq: int = 1_000_000):
+    """
+    Transfer all bytes from a file over SPI using PIO.
+    
+    Args:
+        filepath (str): Path to the file to transmit.
+        freq (int): SPI clock frequency in Hz (default 1 MHz).
+    """
+    tt = DemoBoard.get()
+    # Initialize pins
+    pins = pin_objects(tt)
+    pins_idx = pin_indices()
+    
+    reset = pins['reset']
+    ss = pins['ss']
+    
+    reset.high()
+
+
+    # Calculate PIO frequency (2 cycles per bit, 8 bits per byte)
+    pio_freq = freq * 2 * 8  # e.g., 1 MHz SPI -> 16 MHz PIO
+    print(f"Configuring PIO with frequency: {pio_freq} Hz")
+
+    # Configure PIO state machine
+    sm = StateMachine(0, spi_write, freq=pio_freq, sideset_base=Pin(pins_idx['sck']), 
+                      out_base=Pin(pins_idx['mosi']))
+    
+    # Clear FIFO and ensure state machine is reset
+    sm.restart()
+    sm.active(1)  # Activate state machine
+    print("State machine activated")
+
+    try:
+        # Open file in binary read mode
+        with open(filepath, 'rb') as f:
+            # Set SS low to start SPI transaction
+            fpga_reset(ss, reset)
+            
+            
+            if DoDummyClocks:
+                # release CS
+                ss.high()
+                utime.sleep_us(2000)  
+                # send 8 dummy clocks
+                sm.put(0)
+                
+                # wait until sent
+                utime.sleep_us(20) 
+                while sm.tx_fifo() != 0:
+                    utime.sleep_us(2)
+                    
+                
+                # actually select
+                ss.low()
+                utime.sleep_us(2000) 
+            
+            
+            print("SS low, starting transmission")
+            
+            # Read file in chunks
+            chunk_size = 128  # Reduced chunk size to avoid FIFO overflow
+            byte_count = 0
+            termination_bytes_to_send = 6
+            while True:
+                data = f.read(chunk_size)
+                if not data:  # End of file
+                    for _i in range(termination_bytes_to_send):
+                        
+                        while sm.tx_fifo() != 0:
+                            utime.sleep_us(1)
+                            
+                        sm.put(0)
+                    break
+                        
+                # print(f"Sending {len(data)} bytes")
+                # Send each byte to PIO TX FIFO
+                for byte in data:
+                    # Wait if FIFO is full (tx_fifo() returns free slots, 0 means full)
+                    
+                    sm.put(byte & 0xff, 24) # LEFT shift of the 32 bits, must push up 24 to see byte
+                    while sm.tx_fifo() != 0:
+                        utime.sleep_us(1)  # Small delay to prevent tight loop
+                    byte_count += 1
+                    #if byte_count % 128 == 0:
+                    #    print(f"Sent {byte_count} bytes, TX FIFO free slots: {sm.tx_fifo()}")
+
+            # Wait for FIFO to drain
+            while sm.tx_fifo():
+                print(f"Waiting for FIFO to drain, free slots: {sm.tx_fifo()}")
+                utime.sleep_us(10)
+
+            print(f"Transmission complete, total bytes: {byte_count}")
+
+    except OSError as e:
+        print(f"Error accessing file: {e}")
+    finally:
+        # Deactivate state machine and set SS high
+        sm.active(0)
+        ss.high()
+        sm.restart()
+        sm = None
+        # sck.init(mode=Pin.OUT, pull=None)
+        # mosi.init(mode=Pin.OUT)
+
+        
+        print("State machine deactivated, SS high")
+        
+    
+
+
+
+
+def spi_send(sck, mosi, val, delay_us=1):
+    sck.low()
+    for i in range(8):
+        if val & (1 << (7 - i)):
+            mosi.high()
+        else:
+            mosi.low()
+        sck.high()
+        utime.sleep_us(delay_us)
+        sck.low()
+        utime.sleep_us(delay_us)
+
+        
+def spi_transferBitBang(filepath: str, freq: int = 1_000_000):
+    """
+    Transfer all bytes from a file over SPI using PIO.
+    
+    Args:
+        filepath (str): Path to the file to transmit.
+        freq (int): SPI clock frequency in Hz (default 1 MHz).
+    """
+    # Initialize pins
+    tt = DemoBoard.get()
+    # Initialize pins
+    pins = pin_objects(tt)
+    # pins_idx = pin_indices()
+    
+    reset = pins['reset']
+    ss = pins['ss']
+    sck = pins['sck']
+    mosi = pins['mosi']
+    reset.high()
+
+
+    
+    try:
+        # Open file in binary read mode
+        with open(filepath, 'rb') as f:
+            # Set SS low to start SPI transaction
+            fpga_reset(ss, reset)
+            
+            
+            if DoDummyClocks:
+                # release CS
+                ss.high()
+                utime.sleep_us(2000)  
+                # send 8 dummy clocks
+                spi_send(sck, mosi, 0)
+                
+                # wait until sent
+                utime.sleep_us(20) 
+                    
+                
+                # actually select
+                ss.low()
+                utime.sleep_us(2000) 
+            
+            
+            print("SS low, starting transmission")
+
+            # Read file in chunks
+            chunk_size = 128  # Reduced chunk size to avoid FIFO overflow
+            byte_count = 0
+            termination_bytes_to_send = 6
+            while True:
+                data = f.read(chunk_size)
+                if not data:  # End of file
+                    for _i in range(termination_bytes_to_send):
+                        
+                        spi_send(sck, mosi, 0)
+                    break
+                        
+                # print(f"Sending {len(data)} bytes")
+                # Send each byte to PIO TX FIFO
+                for byte in data:
+                    # Wait if FIFO is full (tx_fifo() returns free slots, 0 means full)
+                    spi_send(sck, mosi, byte)
+                    byte_count += 1
+            print(f"Transmission complete, total bytes: {byte_count}")
+
+    except OSError as e:
+        print(f"Error accessing file: {e}")
+    finally:
+        # Deactivate state machine and set SS high
+        # sck.init(mode=Pin.OUT, pull=None)
+        # mosi.init(mode=Pin.OUT)
+        ss.high()
+        
+        
+        print("State machine deactivated, SS high")
+        
+    return {
+        'ss': ss,
+        'sck': sck,
+        'reset': reset,
+        'mosi': mosi,
+    }
+
+
+# Example usage
+if __name__ == "__main__":
+    # Example: Transfer contents of 'data.bin' at 1 MHz
+    spi_transferPIO("/bitstreams/data.bin", freq=1_000_000)

src/ttboard/fpga/fpga_mux.py

@@ -8,7 +8,7 @@
 from ttboard.boot.shuttle_properties import HardcodedShuttle
 import ttboard.log as logging
 log = logging.getLogger(__name__)
-import ttboard.fpga.fabricfox as fpgaloader
+import ttboard.fpga.fabricfoxv2 as fpgaloader
 class BitStream:
     def __init__(self, loader, filepath:str, name:str, clock_hz:int=100):
         self._filepath = filepath

src/ttboard/log.py

@@ -4,14 +4,14 @@
 @author: Pat Deegan
 @copyright: Copyright (C) 2024 Pat Deegan, https://psychogenic.com
 '''
-from ttboard.util.platform import IsRP2040
+from ttboard.util.platform import IsRP2
 import ttboard.util.colors as colors 
 import ttboard.util.time as time
 import gc 
 RPLoggers = dict()
 DefaultLogLevel = 20 # info by default
 LoggingPrefix = 'BOOT'
-if IsRP2040:
+if IsRP2:
     # no logging support, add something basic
     DEBUG   = 10
     INFO    = 20