Documentation clarification on starting DMA Command Register

[lxylxy123456]

In https://github.com/UCDClassNitta/riscv-console/blob/main/docs/chipset.md#dma-command-register , I think it is better to specify the order of setting each field.
For example, does the instruction have to set all the fields (size and SDT) in one instruction, or can it set the size first and then the SDT?
I used a packed struct to access this register, and I get the following instructions in gcc's -O0, which is probably not going to work.

# a1 = 0x00000001
# a2 = 0x00000050
# a3 = 0x00000000
# a4 = 0x00000000
# a5 = 0x40000028
sb      a1,0(a5)
sb      a2,1(a5)
sb      a3,2(a5)
sb      a4,3(a5)

[lxylxy123456]

Maybe it is also helpful to mention that the DMA status registers should also be read in one instruction. Basically my code below reads the status register in 4 instructions, and get unexpected results.

Web: https://github.com/lxylxy123456/riscv-console/tree/bug15/riscv-bug15
Repo: git@github.com:lxylxy123456/riscv-console.git
Branch: bug15
Folder: riscv-bug15

The program busy waits for DMA until DTA = 0 and then prints Transfer Remaining on the screen. It shows that the transfer remaining is 0xc, instead of 0x0. This is because the status register was updated while reading.

[cjnitta]

Remember that there is a transfer for every cycle. So if it is read/written in multiple cycles the controller will change the portion of the register during a transfer.