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Commit 59df841

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bveq
1 parent 48d60d1 commit 59df841

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2 files changed

+3
-3
lines changed

2 files changed

+3
-3
lines changed

src/main/scala/translating/GTIRBToIR.scala

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -353,7 +353,7 @@ class GTIRBToIR(
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}
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block.address.foreach { case addr =>
356-
val pcCorrectExpr = BinaryExpr(BVEQ, Register("_PC", 64), BitVecLiteral(addr, 64))
356+
val pcCorrectExpr = BinaryExpr(EQ, Register("_PC", 64), BitVecLiteral(addr, 64))
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val assertPC = Assert(pcCorrectExpr, None, Some("pc-tracking"))
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block.statements.append(assertPC)
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}

src/main/scala/util/RunUtils.scala

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1169,8 +1169,8 @@ object RunUtils {
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val pcVar = BVariable("_PC", BitVecBType(64), Scope.Global)
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val r30Var = BVariable("R30", BitVecBType(64), Scope.Global)
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val addrVar = BitVecBLiteral(addr, 64)
1172-
val pcRequires = BinaryBExpr(BVEQ, pcVar, addrVar)
1173-
val pcEnsures = BinaryBExpr(BVEQ, pcVar, Old(r30Var))
1172+
val pcRequires = BinaryBExpr(EQ, pcVar, addrVar)
1173+
val pcEnsures = BinaryBExpr(EQ, pcVar, Old(r30Var))
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val name = proc.procName
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(name -> SubroutineSpec(name, requires = List(pcRequires), ensures = List(pcEnsures)))

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