|
| 1 | +//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// |
| 2 | +// |
| 3 | +// The LLVM Compiler Infrastructure |
| 4 | +// |
| 5 | +// This file is distributed under the University of Illinois Open Source |
| 6 | +// License. See LICENSE.TXT for details. |
| 7 | +// |
| 8 | +//===----------------------------------------------------------------------===// |
| 9 | +// |
| 10 | +// This file contains small standalone helper functions and enum definitions for |
| 11 | +// the X86 target useful for the compiler back-end and the MC libraries. |
| 12 | +// As such, it deliberately does not include references to LLVM core |
| 13 | +// code gen types, passes, etc.. |
| 14 | +// |
| 15 | +//===----------------------------------------------------------------------===// |
| 16 | + |
| 17 | +#ifndef CS_X86_BASEINFO_H |
| 18 | +#define CS_X86_BASEINFO_H |
| 19 | + |
| 20 | +/* Capstone Disassembly Engine */ |
| 21 | +/* By Nguyen Anh Quynh <[email protected]>, 2013-2015 */ |
| 22 | + |
| 23 | +// Enums for memory operand decoding. Each memory operand is represented with |
| 24 | +// a 5 operand sequence in the form: |
| 25 | +// [BaseReg, ScaleAmt, IndexReg, Disp, Segment] |
| 26 | +// These enums help decode this. |
| 27 | +enum { |
| 28 | + X86_AddrBaseReg = 0, |
| 29 | + X86_AddrScaleAmt = 1, |
| 30 | + X86_AddrIndexReg = 2, |
| 31 | + X86_AddrDisp = 3, |
| 32 | + |
| 33 | + /// AddrSegmentReg - The operand # of the segment in the memory operand. |
| 34 | + X86_AddrSegmentReg = 4, |
| 35 | + |
| 36 | + /// AddrNumOperands - Total number of operands in a memory reference. |
| 37 | + X86_AddrNumOperands = 5 |
| 38 | +}; |
| 39 | + |
| 40 | +#endif |
0 commit comments