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PaebbelsPaebbels
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All PoC.sync tests converted to OSVVM-style.
2 parents 6aedc46 + aef72e4 commit 1b38f7a

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-612
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‎tb/RunAllTests.pro‎

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include ./arith/RunAllTests.pro
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include ./bus/RunAllTests.pro
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include ./sync/RunAllTests.pro
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#include ./cache/RunAllTests.pro
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#include ./common/RunAllTests.pro
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#include ./dstruct/RunAllTests.pro

‎tb/sync/Bits/RunAllTests.pro‎

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# =============================================================================
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# Authors:
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# Gustavo Martin
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#
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# License:
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# =============================================================================
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# Copyright 2025-2025 The PoC-Library Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# =============================================================================
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analyze sync_Bits_TestController.vhdl
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analyze sync_Bits_TestHarness.vhdl
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RunTest sync_Bits_Simple.vhdl

‎tb/sync/Bits/sync_Bits_Simple.vhdl‎

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-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
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-- vim: tabstop=2:shiftwidth=2:noexpandtab
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-- kate: tab-width 2; replace-tabs off; indent-width 2;
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-- =============================================================================
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-- Authors: Patrick Lehmann
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-- Gustavo Martin
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--
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-- Entity: sync_Bits_TestController (Simple architecture)
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--
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-- Description:
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-- -------------------------------------
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-- OSVVM simple test for flag signal synchronizer.
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-- Tests that signals propagate correctly across clock domains.
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 The PoC-Library Authors
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-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
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-- Chair of VLSI-Design, Diagnostics and Architecture
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library osvvm;
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context osvvm.OsvvmContext;
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library PoC;
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use PoC.utils.all;
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architecture Simple of sync_Bits_TestController is
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signal TestDone : integer_barrier := 1;
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constant TCID : AlertLogIDType := NewID("TestCtrl");
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constant INIT : std_logic_vector(Sync_out'range) := (others => '0');
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begin
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ControlProc : process
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constant ProcID : AlertLogIDType := NewID("ControlProc", TCID);
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constant TIMEOUT : time := 10 ms;
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begin
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SetTestName("sync_Bits_Simple");
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SetLogEnable(PASSED, FALSE);
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SetLogEnable(INFO, FALSE);
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SetLogEnable(DEBUG, FALSE);
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wait for 0 ns; wait for 0 ns;
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TranscriptOpen;
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SetTranscriptMirror(TRUE);
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wait until Reset = '0';
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ClearAlerts;
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WaitForBarrier(TestDone, TIMEOUT);
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AlertIf(ProcID, now >= TIMEOUT, "Test finished due to timeout");
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AlertIf(ProcID, GetAffirmCount < 1, "Test is not Self-Checking");
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EndOfTestReports(ReportAll => TRUE);
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std.env.stop;
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end process;
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StimuliProc : process
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constant ProcID : AlertLogIDType := NewID("StimuliProc", TCID);
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begin
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-- Initialize
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Sync_in <= INIT;
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wait until Reset = '0';
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WaitForClock(Clock1, 4);
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-- Toggle input several times with different patterns
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Sync_in <= "1";
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WaitForClock(Clock1, 2);
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Sync_in <= "0";
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WaitForClock(Clock1, 2);
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Sync_in <= "1";
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WaitForClock(Clock1, 2);
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Sync_in <= "0";
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WaitForClock(Clock1, 6);
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Sync_in <= "1";
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WaitForClock(Clock1, 16);
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Sync_in <= "0";
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WaitForClock(Clock1, 2);
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Sync_in <= "1";
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WaitForClock(Clock1, 2);
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Sync_in <= "0";
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WaitForClock(Clock1, 6);
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wait;
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end process;
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CheckerProc : process
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constant ProcID : AlertLogIDType := NewID("CheckerProc", TCID);
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variable toggled : natural := 0;
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variable Sync_out_old : std_logic_vector(Sync_out'range);
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begin
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wait until Reset = '0';
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WaitForClock(Clock2);
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-- Check initial value
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AffirmIf(ProcID, Sync_out = INIT, "Initial value should be " & to_string(INIT));
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Sync_out_old := Sync_out;
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-- Count toggle events for a maximum of 50 clock cycles
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for i in 1 to 50 loop
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WaitForClock(Clock2);
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if Sync_out /= Sync_out_old then
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toggled := toggled + 1;
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Sync_out_old := Sync_out;
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end if;
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end loop;
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-- Should see 8 toggle events based on stimuli
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AffirmIf(ProcID, toggled = 8,
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"Expected 8 toggle events, got " & integer'image(toggled));
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WaitForBarrier(TestDone);
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wait;
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end process;
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end architecture;
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configuration sync_Bits_Simple of sync_Bits_TestHarness is
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for TestHarness
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for TestCtrl : sync_Bits_TestController
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use entity work.sync_Bits_TestController(Simple);
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end for;
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end for;
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end configuration;

‎tb/sync/Bits/sync_Bits_TestController.vhdl‎

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-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
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-- vim: tabstop=2:shiftwidth=2:noexpandtab
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-- kate: tab-width 2; replace-tabs off; indent-width 2;
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-- =============================================================================
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-- Authors: Patrick Lehmann
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-- Gustavo Martin
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--
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-- Entity: sync_Bits_TestController
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--
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-- Description:
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-- -------------------------------------
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-- OSVVM test controller entity for flag signal synchronizer
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 The PoC-Library Authors
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-- Copyright 2007-2016 Technische Universitaet Dresden - Germany
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-- Chair of VLSI-Design, Diagnostics and Architecture
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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library osvvm;
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context osvvm.OsvvmContext;
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entity sync_Bits_TestController is
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port (
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Clock1 : in std_logic;
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Clock2 : in std_logic;
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Reset : in std_logic;
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Sync_in : out std_logic_vector;
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Sync_out : in std_logic_vector
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);
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end entity;

‎tb/sync/Bits/sync_Bits_TestHarness.vhdl‎

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-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
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-- vim: tabstop=2:shiftwidth=2:noexpandtab
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-- kate: tab-width 2; replace-tabs off; indent-width 2;
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-- =============================================================================
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-- Authors: Gustavo Martin
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--
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-- Entity: sync_Bits_TestHarness
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--
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-- Description:
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-- -------------------------------------
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-- OSVVM testbench harness for flag signal synchronizer
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--
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-- License:
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-- =============================================================================
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-- Copyright 2025-2025 The PoC-Library Authors
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- =============================================================================
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library osvvm;
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context osvvm.OsvvmContext;
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library PoC;
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entity sync_Bits_TestHarness is
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end entity;
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architecture TestHarness of sync_Bits_TestHarness is
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-- Clock periods (100 MHz and 60 MHz)
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constant TPERIOD_CLOCK_1 : time := 10 ns;
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constant TPERIOD_CLOCK_2 : time := 16.667 ns;
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constant BITS : positive := 1;
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constant INIT : std_logic_vector(BITS - 1 downto 0) := (others => '0');
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signal Clock1 : std_logic := '1';
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signal Clock2 : std_logic := '1';
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signal Reset : std_logic := '1';
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signal Sync_in : std_logic_vector(BITS - 1 downto 0);
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signal Sync_out : std_logic_vector(BITS - 1 downto 0);
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component sync_Bits_TestController is
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port (
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Clock1 : in std_logic;
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Clock2 : in std_logic;
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Reset : in std_logic;
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Sync_in : out std_logic_vector;
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Sync_out : in std_logic_vector
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);
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end component;
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begin
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Osvvm.ClockResetPkg.CreateClock(
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Clk => Clock1,
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Period => TPERIOD_CLOCK_1
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);
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Osvvm.ClockResetPkg.CreateClock(
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Clk => Clock2,
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Period => TPERIOD_CLOCK_2
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);
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Osvvm.ClockResetPkg.CreateReset(
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Reset => Reset,
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ResetActive => '1',
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Clk => Clock1,
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Period => 5 * TPERIOD_CLOCK_1,
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tpd => 0 ns
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);
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DUT : entity PoC.sync_Bits
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generic map (
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BITS => BITS,
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INIT => INIT
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)
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port map (
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Clock => Clock2,
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Input => Sync_in,
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Output => Sync_out
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);
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TestCtrl : component sync_Bits_TestController
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port map (
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Clock1 => Clock1,
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Clock2 => Clock2,
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Reset => Reset,
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Sync_in => Sync_in,
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Sync_out => Sync_out
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);
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end architecture;

‎tb/sync/Command/RunAllTests.pro‎

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# =============================================================================
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# Authors:
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# Gustavo Martin
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#
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# License:
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# =============================================================================
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# Copyright 2025-2025 The PoC-Library Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# =============================================================================
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analyze sync_Command_TestController.vhdl
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analyze sync_Command_TestHarness.vhdl
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RunTest sync_Command_Simple.vhdl

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