Removed Testcontroller package for PoC.arith.div.

Author: Paebbels

tb/arith/addw/arith_addw_TestController_pkg.vhdl

@@ -41,12 +41,12 @@ package arith_addw_TestController_pkg is
 
   constant N : positive := 9;
   constant K : positive := 2;
-  
+
   subtype tArch_test is tArch;
   subtype tSkip_test is tSkipping;
-  
+
   subtype word is std_logic_vector(N-1 downto 0);
   type word_vector is array(tArch_test, tSkip_test, boolean) of word;
   type carry_vector is array(tArch_test, tSkip_test, boolean) of std_logic;
 
-end package arith_addw_TestController_pkg;
+end package;

tb/arith/div/RunAllTests.pro

@@ -1,5 +1,5 @@
 # =============================================================================
-# Authors: 
+# Authors:
 #   Gustavo Martin
 # License:
 # =============================================================================
@@ -18,7 +18,6 @@
 # limitations under the License.
 # =============================================================================
 
-analyze arith_div_TestController_pkg.vhdl
 analyze arith_div_TestController.vhdl
 analyze arith_div_TestHarness.vhdl
 

tb/arith/div/arith_div_Simple.vhdl

@@ -42,9 +42,6 @@ use     PoC.strings.all;
 library osvvm;
 context osvvm.OsvvmContext;
 
-library tb_arith;
-use     tb_arith.arith_div_TestController_pkg.all;
-
 architecture Simple of arith_div_TestController is
   signal TestDone : integer_barrier := 1;
   constant TCID : AlertLogIDType := NewID("AddWTest");
@@ -87,12 +84,12 @@ begin
     variable Random : RandomPType;
 
     procedure test(aval, dval : in integer) is
-      variable QQ : T_SLVV(1 to 2*MAX_POW)(A_BITS-1 downto 0);
-      variable RR : T_SLVV(1 to 2*MAX_POW)(D_BITS-1 downto 0);
-      variable ZZ : std_logic_vector(1 to 2*MAX_POW);
+      variable QQ : T_SLVV(Z'range)(A'range);
+      variable RR : T_SLVV(Z'range)(D'range);
+      variable ZZ : std_logic_vector(Z'range);
 
       type boolean_vector is array(positive range<>) of boolean;
-      variable done : boolean_vector(1 to 2*MAX_POW);
+      variable done : boolean_vector(Ready'range);
       variable all_done : boolean;
     begin
       -- Start
@@ -106,7 +103,7 @@ begin
       A     <= (others => '-');
       D     <= (others => '-');
       done  := (others => false);
-      
+
       loop
         all_done := true;
         for i in done'range loop
@@ -131,7 +128,7 @@ begin
         else
           AffirmIf(ZZ(i) = '0', "INST=" & integer'image(i) & " Zero flag check failed: " & integer'image(aval) & "/" & integer'image(dval));
           AffirmIf(to_integer(unsigned(QQ(i)))*dval + to_integer(unsigned(RR(i))) = aval,
-                   "INST=" & integer'image(i) & " Result check failed: " & integer'image(aval) & "/" & integer'image(dval) & 
+                   "INST=" & integer'image(i) & " Result check failed: " & integer'image(aval) & "/" & integer'image(dval) &
                    " /= " & integer'image(to_integer(unsigned(QQ(i)))) & " R " & integer'image(to_integer(unsigned(RR(i)))));
         end if;
       end loop;
@@ -147,19 +144,19 @@ begin
 
     -- Reset
     wait until Reset = '0';
-    
+
     -- Boundary Conditions
     test(0, 0);
-    test(0, 2**D_BITS-1);
+    test(0, 2**D'length - 1);
     test(0, 1);
     test(1, 0);
     test(2, 0);
-    test(2**A_BITS-1, 0);
-    test(2**A_BITS-1, 2**D_BITS-1);
+    test(2**A'length - 1, 0);
+    test(2**A'length - 1, 2**D'length - 1);
 
     -- Run Random Tests
     for i in 0 to 1023 loop
-      test(Random.Uniform(0, 2**A_BITS-1), Random.Uniform(0, 2**D_BITS-1));
+      test(Random.Uniform(0, 2**A'length - 1), Random.Uniform(0, 2**D'length - 1));
     end loop;
 
     -- End of Test

tb/arith/div/arith_div_TestController.vhdl

@@ -42,20 +42,18 @@ use     PoC.strings.all;
 library osvvm;
 context osvvm.OsvvmContext;
 
-library tb_arith;
-use     tb_arith.arith_div_TestController_pkg.all;
 
 entity arith_div_TestController is
   port (
     Clock : in std_logic;
     Reset : in std_logic;
 
     Start : out std_logic;
-    Ready : in  std_logic_vector(1 to 2*MAX_POW);
-    A     : out std_logic_vector(A_BITS-1 downto 0);
-    D     : out std_logic_vector(D_BITS-1 downto 0);
-    Q     : in  T_SLVV(1 to 2*MAX_POW)(A_BITS-1 downto 0);
-    R     : in  T_SLVV(1 to 2*MAX_POW)(D_BITS-1 downto 0);
-    Z     : in  std_logic_vector(1 to 2*MAX_POW)
+    Ready : in  std_logic_vector;
+    A     : out std_logic_vector;
+    D     : out std_logic_vector;
+    Q     : in  T_SLVV;
+    R     : in  T_SLVV;
+    Z     : in  std_logic_vector
   );
 end entity;

tb/arith/div/arith_div_TestController_pkg.vhdl

@@ -43,15 +43,16 @@ use     PoC.physical.all;
 library osvvm;
 context osvvm.OsvvmContext;
 
-library tb_arith;
-use     tb_arith.arith_div_TestController_pkg.all;
-
 entity arith_div_TestHarness is
 end entity;
 
 architecture tb of arith_div_TestHarness is
   constant CLOCK_PERIOD : time := 10 ns;
 
+  constant A_BITS  : positive := 13;
+  constant D_BITS  : positive := 4;
+  constant MAX_POW : positive := 3;
+
   signal Clock : std_logic;
   signal Reset : std_logic;
 
@@ -68,12 +69,12 @@ architecture tb of arith_div_TestHarness is
       Clock : in std_logic;
       Reset : in std_logic;
       Start : out std_logic;
-      Ready : in  std_logic_vector(1 to 2*MAX_POW);
-      A     : out std_logic_vector(A_BITS-1 downto 0);
-      D     : out std_logic_vector(D_BITS-1 downto 0);
-      Q     : in  T_SLVV(1 to 2*MAX_POW)(A_BITS-1 downto 0);
-      R     : in  T_SLVV(1 to 2*MAX_POW)(D_BITS-1 downto 0);
-      Z     : in  std_logic_vector(1 to 2*MAX_POW)
+      Ready : in  std_logic_vector;
+      A     : out std_logic_vector;
+      D     : out std_logic_vector;
+      Q     : in  T_SLVV;
+      R     : in  T_SLVV;
+      Z     : in  std_logic_vector
     );
   end component;