Upstream update available: designs/src/litepci/dev/repo

• Pinned: 95f4731173db01158638b14a7eb4a679df1c2575 (2026-05-11)
• Upstream: 2fb7277c51c9c879f6f7ffbfa56807fcd3600ab1 (2026-06-12)
• Commits behind: 25
• Days stale: 32

Severity: MODERATE

Several RTL-affecting bug fixes in the TLP datapath plus DMA/software
fixes and test reorganization. Fixes are localized, no API/architecture
change.

What changed

• axis_adapters fixes: SAxisRQAdapter 256-bit requester-descriptor
  addr-at-DW0 fix, 3DW/4DW request handling, 512-bit RQ 4DW mapping fix.
• tlp: packetizer keeps 128-bit 4DW payload in DATA; controller retires
  requests / frees tags on error completions (UR/CA) to fix deadlock.
• frontend/dma: reset reader/writer data converters with the DMA.
• software: shared DMA device fd, PCIe rescan utility, coherent-buffer
  mmap fix, liteuart RX/TX polling robustness.
• Test suite split (slow vs default CI), opt-in VCD, canonical imports,
  CSR aliases, version bump 2026.04.

Recommendation

Update at next refresh. The axis_adapters RQ-descriptor and
error-completion deadlock fixes are genuine TLP correctness improvements;
worth picking up if litepci closure exercises those paths. Re-validate
litepci (asap7/nangate45) after the bump; note the pre-existing
unconstrained forwarded-clock QoR caveat is unrelated.

Last refreshed: 2026-06-15 11:00:24 UTC