improvements ddr clk

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>

Author: maass-hamburg

litespi/phy/generic_ddr_with_clk.py

@@ -125,24 +125,19 @@ def __init__(self, pads, flash, clock_domain, default_divisor, cs_delay):
                 4:  dq_o[1].eq(sr_out[-4:]),
                 8:  dq_o[1].eq(sr_out[-8:]),
             }),
-            Case(sink.width, {
-                1 : sr_out_shifted.eq(Cat(Signal(1), sr_out[:-1])),
-                2 : sr_out_shifted.eq(Cat(Signal(2), sr_out[:-2])),
-                4 : sr_out_shifted.eq(Cat(Signal(4), sr_out[:-4])),
-                8 : sr_out_shifted.eq(Cat(Signal(8), sr_out[:-8])),
-            }),
+            sr_out_shifted.eq(sr_out << sink.width),
             sr_out_loaded.eq(sink.data << (len(sink.data) - sink.len))
         ]
         self.sync += If(sr_out_load,
+            sr_in.eq(0),
             sr_out.eq(sr_out_loaded),
             Case(sink.width, {
                 1:  dq_o[0].eq(sr_out_loaded[-1:]),
                 2:  dq_o[0].eq(sr_out_loaded[-2:]),
                 4:  dq_o[0].eq(sr_out_loaded[-4:]),
                 8:  dq_o[0].eq(sr_out_loaded[-8:]),
             }),
-        )
-        self.sync += If(sr_out_shift[0],
+        ).Elif(sr_out_shift[0],
             Case(sink.width, {
                 1:  dq_o[0].eq(sr_out_shifted[-1:]),
                 2:  dq_o[0].eq(sr_out_shifted[-2:]),
@@ -153,7 +148,7 @@ def __init__(self, pads, flash, clock_domain, default_divisor, cs_delay):
         ).Elif(sr_out_shift[1],
             dq_o[0].eq(dq_o[1]),
             sr_out.eq(sr_out_shifted),
-        ).Elif(~sr_out_load,
+        ).Else(
             dq_o[0].eq(dq_o[1]),
         )