phy: improve XFER-END for SDR and DRR

improve XFER-END for SDR and DRR

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>

Author: maass-hamburg

litespi/phy/generic_ddr_with_clk.py

@@ -223,6 +223,11 @@ def __init__(self, pads, flash, clock_domain, default_divisor, cs_delay, extra_l
                 sr_in_shift.eq(clkgen.posedge_reg2),
                 If(clkgen.posedge_reg2,
                     NextValue(sr_in_cnt, sr_in_cnt - sink.width),
+                    If(sr_in_cnt == sink.width,
+                       sink.ready.eq(1),
+                       # Send Status/Data to Core.
+                       NextState("SEND-STATUS-DATA"),
+                    ),
                 ),
             ),
         )

litespi/phy/generic_sdr.py

@@ -206,6 +206,11 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay,
                 sr_in_shift.eq(clkgen.posedge_reg2),
                 If(clkgen.posedge_reg2,
                     NextValue(sr_in_cnt, sr_in_cnt - sink.width),
+                    If(sr_in_cnt == sink.width,
+                       sink.ready.eq(1),
+                       # Send Status/Data to Core.
+                       NextState("SEND-STATUS-DATA"),
+                    ),
                 ),
             ),
         )