phy: start cs timer already when cs is falling

start cs timer already when cs is falling,
instead of when it's going to be used.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>

Author: maass-hamburg

litespi/cscontrol.py

@@ -11,17 +11,33 @@
 from litex.build.io import SDROutput
 
 class LiteSPICSControl(LiteXModule):
-    def __init__(self, pads, cs, cs_delay):
+    def __init__(self, pads, cs, cs_delay=10, with_sdr_cs=True, **kwargs):
         self.enable = enable = Signal()
         cs_n = Signal().like(pads.cs_n)
+        last_cs = Signal()
 
         self.timer = timer  = WaitTimer(cs_delay + 1) # Ensure cs_delay cycles between XFers.
-        
-        self.comb += timer.wait.eq(cs != 0)
-        self.comb += enable.eq(timer.done)
+
+        if len(pads.cs_n) > 1:
+            # Remember last active CS when multiple CS lines are used, so we only wait when
+            # the same CS line is active again
+            last_active_cs = Signal(len(cs))
+            self.sync += If(enable, last_active_cs.eq(cs))
+
+            enable_cond = timer.done | (last_active_cs != cs)
+        else:
+            enable_cond = timer.done
+
+        self.sync += last_cs.eq(cs != 0)
+
+        self.comb += timer.wait.eq(~((cs == 0) & last_cs)) # Reset wait on falling edge of cs
+        self.comb += enable.eq((cs != 0) & enable_cond)
         self.comb += cs_n.eq(~(Replicate(enable, len(pads.cs_n)) & cs))
 
-        self.specials += SDROutput(
-            i = cs_n,
-            o = pads.cs_n
-        )
+        if with_sdr_cs:
+            self.specials += SDROutput(
+                i = cs_n,
+                o = pads.cs_n
+            )
+        else:
+            self.comb += pads.cs_n.eq(cs_n)

litespi/phy/generic.py

@@ -57,12 +57,12 @@ class LiteSPIPHY(LiteXModule):
         Flash CS signal from ``LiteSPIPHYCore``.
     """
 
-    def __init__(self, pads, flash, device="xc7", clock_domain="sys", default_divisor=9, cs_delay=10, rate="1:1", **kwargs):
+    def __init__(self, pads, flash, device="xc7", clock_domain="sys", rate="1:1", **kwargs):
         assert rate in ["1:1", "1:2"]
         if rate == "1:1":
-            phy = LiteSPISDRPHYCore(pads, flash, device, clock_domain, default_divisor, cs_delay, **kwargs)
+            phy = LiteSPISDRPHYCore(pads, flash, device, clock_domain, **kwargs)
         if rate == "1:2":
-            phy = LiteSPIDDRPHYCore2(pads, flash, clock_domain, default_divisor, cs_delay, **kwargs)
+            phy = LiteSPIDDRPHYCore2(pads, flash, clock_domain, **kwargs)
 
         self.flash = flash
 

litespi/phy/generic_ddr.py

@@ -52,7 +52,7 @@ class LiteSPIDDRPHYCore(LiteXModule):
     cs : Signal(), in
         Flash CS signal.
     """
-    def __init__(self, pads, flash, cs_delay, extra_latency=0, **kwargs):
+    def __init__(self, pads, flash, extra_latency=0, **kwargs):
         self.source = source = stream.Endpoint(spi_phy2core_layout)
         self.sink   = sink   = stream.Endpoint(spi_core2phy_layout)
         self.cs              = Signal().like(pads.cs_n)
@@ -74,7 +74,7 @@ def __init__(self, pads, flash, cs_delay, extra_latency=0, **kwargs):
         self.clkgen = clkgen = DDRLiteSPIClkGen(pads)
 
         # CS control.
-        self.cs_control = cs_control = LiteSPICSControl(pads, self.cs, cs_delay)
+        self.cs_control = cs_control = LiteSPICSControl(pads, self.cs, **kwargs)
 
         dq_o  = Array([Signal(len(pads.dq)) for _ in range(2)])
         dq_i  = Array([Signal(len(pads.dq)) for _ in range(2)])

litespi/phy/generic_ddr_with_clk.py

@@ -56,7 +56,7 @@ class LiteSPIDDRPHYCore2(LiteXModule):
     clk_divisor : CSRStorage
         Register which holds a clock divisor value applied to clkgen.
     """
-    def __init__(self, pads, flash, clock_domain, default_divisor, cs_delay, extra_latency=0, **kwargs):
+    def __init__(self, pads, flash, clock_domain, default_divisor=9, extra_latency=0, **kwargs):
         self.source           = source = stream.Endpoint(spi_phy2core_layout)
         self.sink             = sink   = stream.Endpoint(spi_core2phy_layout)
         self.cs               = Signal().like(pads.cs_n)
@@ -89,7 +89,7 @@ def __init__(self, pads, flash, clock_domain, default_divisor, cs_delay, extra_l
         self.clkgen = clkgen = LiteSPIClkGen2(pads, div_width=len(sink.clk_div), extra_latency=2*extra_latency)
 
         # CS control.
-        self.cs_control = cs_control = LiteSPICSControl(pads, self.cs, cs_delay)
+        self.cs_control = cs_control = LiteSPICSControl(pads, self.cs, **kwargs)
 
         # Only Clk Divisor when not active or when set by core.
         self.sync += [

litespi/phy/generic_sdr.py

@@ -59,7 +59,7 @@ class LiteSPISDRPHYCore(LiteXModule):
     clk_divisor : CSRStorage
         Register which holds a clock divisor value applied to clkgen.
     """
-    def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay, extra_latency=0, **kwargs):
+    def __init__(self, pads, flash, device, clock_domain, default_divisor=9, extra_latency=0, **kwargs):
         self.source           = source = stream.Endpoint(spi_phy2core_layout)
         self.sink             = sink   = stream.Endpoint(spi_core2phy_layout)
         self.cs               = Signal().like(pads.cs_n)
@@ -90,7 +90,7 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay,
         self.clkgen = clkgen = LiteSPIClkGen(pads, device, div_width=len(sink.clk_div), extra_latency=extra_latency)
 
         # CS control.
-        self.cs_control = cs_control = LiteSPICSControl(pads, self.cs, cs_delay)
+        self.cs_control = cs_control = LiteSPICSControl(pads, self.cs, **kwargs)
 
         # Only Clk Divisor when not active or when set by core.
         self.sync += [