VUnit+ghdl simulator fails on system verilog code. Expected behavior?

[russelljjarvis]

Hi @marcoieni,

I was running VUnit using this repository as a base, combined with github actions and simple but different source code.

The simulated verification fails to compile with the code and I think it hits an error in its own source code (see below).

Is it possible that the problem is system verilog is not supported/expected or something else?

Thanks for your help.

https://github.com/russelljjarvis/vunit_action/runs/7051687300?check_suite_focus=true

/usr/local/lib/python3.9/dist-packages/vunit/vhdl/check/src/check.vhd:1828:16:warning: declaration of "expected_events" hides variable "expected_events" [-Whide]
      constant expected_events   : in boolean_vector;
               ^
/usr/local/lib/python3.9/dist-packages/vunit/vhdl/check/src/check.vhd:1829:16:warning: declaration of "event_sequence" hides signal interface "event_sequence" [-Whide]
      constant event_sequence    : in std_logic_vector) is
               ^
Compiling into lib:       test/src/adder_8in.v                                                                                            failed
File type not supported by ghdl simulator
Compile failed
Error: Process completed with exit code 1.

[marcoieni]

Hi Russell, sorry but I have done this projects several time ago.
I haven't used it since then and I don't have the time to support it anymore :(