diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.cache/wt/gui_handlers.wdf b/hardware/Vivado/E-ELEMENTS/RISC-V.cache/wt/gui_handlers.wdf new file mode 100644 index 0000000..d068f61 --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.cache/wt/gui_handlers.wdf @@ -0,0 +1,41 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6162737472616374636f6d62696e656470616e656c5f72656d6f76655f73656c65637465645f656c656d656e7473:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f68646c5f6e65746c6973745f626c6f636b5f64657369676e:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f6f725f6372656174655f636f6e73747261696e745f66696c6573:31:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f63616e63656c:35:00:00 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+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.hw/RISC-V.lpr b/hardware/Vivado/E-ELEMENTS/RISC-V.hw/RISC-V.lpr new file mode 100644 index 0000000..c52c42d --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.hw/RISC-V.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.hw/hw_1/hw.xml b/hardware/Vivado/E-ELEMENTS/RISC-V.hw/hw_1/hw.xml new file mode 100644 index 0000000..d3dac31 --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.hw/hw_1/hw.xml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/constrs_1/new/ARTIX7.xdc b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/constrs_1/new/ARTIX7.xdc new file mode 100644 index 0000000..ac273f6 --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/constrs_1/new/ARTIX7.xdc @@ -0,0 +1,99 @@ + +## Clock signal + +##RGB LEDs +#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { LEDG[0] }]; #IO_L19N_T3_VREF_35 Sch=led0_g +#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { LEDR[0] }]; #IO_L19P_T3_35 Sch=led0_r +#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { LEDG[1] }]; #IO_L21P_T3_DQS_35 Sch=led1_g +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { LEDR[1] }]; #IO_L20N_T3_35 Sch=led1_r +#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { LEDB[2] }]; #IO_L21N_T3_DQS_35 Sch=led2_b +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { LEDG[2] }]; #IO_L22N_T3_35 Sch=led2_g +#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { LEDR[2] }]; #IO_L22P_T3_35 Sch=led2_r +#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { LEDB[3] }]; #IO_L23P_T3_35 Sch=led3_b +#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { LEDG[3] }]; #IO_L24P_T3_35 Sch=led3_g +#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { LEDR[3] }]; #IO_L23N_T3_35 Sch=led3_r + +##LEDs + +##USB-UART Interface + +##Quad SPI Flash +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { FLASH_CS }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { FLASH_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { FLASH_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { FLASH_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { FLASH_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] + +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports CLK_50] +set_property IOSTANDARD LVCMOS33 [get_ports UART_RXD] +set_property IOSTANDARD LVCMOS33 [get_ports UART_TXD] +set_property IOSTANDARD LVCMOS33 [get_ports VGA_HS] +set_property IOSTANDARD LVCMOS33 [get_ports VGA_VS] +set_property PACKAGE_PIN D8 [get_ports {VGA_G[3]}] +set_property PACKAGE_PIN A3 [get_ports {VGA_G[2]}] +set_property PACKAGE_PIN A4 [get_ports {VGA_G[1]}] +set_property PACKAGE_PIN B6 [get_ports {VGA_G[0]}] +set_property PACKAGE_PIN E7 [get_ports {VGA_B[3]}] +set_property PACKAGE_PIN A1 [get_ports {VGA_B[2]}] +set_property PACKAGE_PIN B1 [get_ports {VGA_B[1]}] +set_property PACKAGE_PIN C7 [get_ports {VGA_B[0]}] +set_property PACKAGE_PIN C5 [get_ports {VGA_R[2]}] +set_property PACKAGE_PIN C6 [get_ports {VGA_R[1]}] +set_property PACKAGE_PIN F5 [get_ports {VGA_R[0]}] +set_property PACKAGE_PIN P17 [get_ports CLK_50] +set_property PACKAGE_PIN B7 [get_ports {VGA_R[3]}] + + + +set_property PACKAGE_PIN N5 [get_ports UART_RXD] +set_property PACKAGE_PIN T4 [get_ports UART_TXD] +set_property PACKAGE_PIN D7 [get_ports VGA_HS] +set_property PACKAGE_PIN D5 [get_ports VGA_VS] + +set_property IOSTANDARD LVCMOS33 [get_ports {DIG[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DIG[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DIG[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DIG[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DIG[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DIG[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DIG[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {DIG[0]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SEL[7]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SEL[6]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SEL[5]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SEL[4]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SEL[3]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SEL[2]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SEL[1]}] +set_property IOSTANDARD LVCMOS33 [get_ports {SEL[0]}] +set_property PACKAGE_PIN D4 [get_ports {DIG[0]}] +set_property PACKAGE_PIN H2 [get_ports {DIG[7]}] +set_property PACKAGE_PIN D2 [get_ports {DIG[6]}] +set_property PACKAGE_PIN E2 [get_ports {DIG[5]}] +set_property PACKAGE_PIN F3 [get_ports {DIG[4]}] +set_property PACKAGE_PIN F4 [get_ports {DIG[3]}] +set_property PACKAGE_PIN D3 [get_ports {DIG[2]}] +set_property PACKAGE_PIN E3 [get_ports {DIG[1]}] +set_property PACKAGE_PIN J2 [get_ports {SEL[5]}] +set_property PACKAGE_PIN K2 [get_ports {SEL[4]}] +set_property PACKAGE_PIN F6 [get_ports {SEL[3]}] +set_property PACKAGE_PIN G4 [get_ports {SEL[2]}] + + + +set_property PACKAGE_PIN G3 [get_ports {SEL[1]}] +set_property PACKAGE_PIN J4 [get_ports {SEL[0]}] +set_property PACKAGE_PIN J3 [get_ports {SEL[6]}] +set_property PACKAGE_PIN H4 [get_ports {SEL[7]}] diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/char8x16_rom.sv b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/char8x16_rom.sv new file mode 100644 index 0000000..040e9f9 --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/char8x16_rom.sv @@ -0,0 +1,2074 @@ +// +// 存放所有 ASCII 字符的字码 +// 该ROM自动综合成Block RAM +// 每个字符为8*16个像素，8列16行 +// 机制：每次读取时需要输入一个 7bit ASCII 值和一个 4bit 行号，共同组成12bit地址 +// ASCII值表示想要读取的字符的ASCII码 +// 4bit行号的取值范围是0~15，指定了想要读取该字符的哪一行像素。 +// 输出8bit，即该字符这一行的8个像素。0代表黑色，1代表白色（黑底白字） +// 因此该模块只是一个普通的8bit数据总线，12bit地址总线的ROM而已 + +module char8x16_rom( + input logic clk, + input logic [11:0] addr, + output logic [ 7:0] data +); + +wire [0:2047] [7:0] rom_cell = { + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h18, + 8'h18, + 8'h18, + 8'h18, + 8'h18, + 8'h18, + 8'h10, + 8'h00, + 8'h10, + 8'h18, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h2c, + 8'h24, + 8'h24, + 8'h24, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 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8'h00, + 8'hc2, + 8'h42, + 8'h66, + 8'h24, + 8'h2c, + 8'h18, + 8'h18, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h83, + 8'h83, + 8'hda, + 8'h5a, + 8'h7a, + 8'h66, + 8'h66, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h46, + 8'h64, + 8'h38, + 8'h18, + 8'h38, + 8'h64, + 8'h46, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'hc2, + 8'h42, + 8'h66, + 8'h24, + 8'h2c, + 8'h38, + 8'h18, + 8'h18, + 8'h0c, + 8'h07, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h7e, + 8'h60, + 8'h30, + 8'h18, + 8'h08, + 8'h04, + 8'h7e, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h70, + 8'h18, + 8'h08, + 8'h08, + 8'h08, + 8'h0c, + 8'h0e, + 8'h08, + 8'h08, + 8'h08, + 8'h08, + 8'h18, + 8'h70, + 8'h00, + 8'h00, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h00, + 8'h00, + 8'h00, + 8'h0c, + 8'h18, + 8'h10, + 8'h10, + 8'h10, + 8'h30, + 8'h70, + 8'h10, + 8'h10, + 8'h10, + 8'h10, + 8'h18, + 8'h0c, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h8e, + 8'hd2, + 8'h60, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00, + 8'h00 +}; + +always @ (posedge clk) + if(addr[11]) + data <= 8'h0; + else + data <= rom_cell[addr[10:0]]; + +endmodule diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/core_alu.sv b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/core_alu.sv new file mode 100644 index 0000000..bae236d --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/core_alu.sv @@ -0,0 +1,85 @@ +module core_alu( + input logic [ 6:0] i_opcode, i_funct7, + input logic [ 2:0] i_funct3, + input logic [31:0] i_num1u, i_num2u, i_pc, i_immu, + output logic o_branch_jalr, + output logic [31:0] o_res, o_branch_jalr_target +); +logic [ 4:0] shamt_rs, shamt_imm; +logic [31:0] num1_plus_imm, pc_plus_imm; +logic signed [31:0] i_num1s, i_num2s, i_imms; + +assign shamt_imm = i_immu[4:0]; +assign shamt_rs = i_num2u[4:0]; +assign num1_plus_imm = i_num1u + i_immu; +assign pc_plus_imm = i_pc + i_immu; +assign i_num1s = i_num1u; +assign i_num2s = i_num2u; +assign i_imms = i_immu; + +always_comb + case(i_opcode) + 7'b1100111 : begin // JALR + o_branch_jalr <= 1'b1; + o_branch_jalr_target <= num1_plus_imm; + end + 7'b1100011 : begin // BRANCH�? + case(i_funct3) + 3'b000 : o_branch_jalr <= (i_num1u == i_num2u); // BEQ + 3'b001 : o_branch_jalr <= (i_num1u != i_num2u); // BNE + 3'b100 : o_branch_jalr <= (i_num1s < i_num2s); // BLT + 3'b101 : o_branch_jalr <= (i_num1s >= i_num2s); // BGE + 3'b110 : o_branch_jalr <= (i_num1u < i_num2u); // BLTU + 3'b111 : o_branch_jalr <= (i_num1u >= i_num2u); // BGEU + default: o_branch_jalr <= 1'b0; + endcase + o_branch_jalr_target <= pc_plus_imm; + end + default : begin // 不跳�? + o_branch_jalr <= 1'b0; + o_branch_jalr_target <= 0; + end + endcase + +always_comb + casex({i_funct7,i_funct3,i_opcode}) + // JAL类与JALR�? + 17'bxxxxxxx_xxx_110x111 : o_res <= i_pc + 4; // JAL, JALR + // LUI�? + 17'bxxxxxxx_xxx_0110111 : o_res <= i_immu; // LUI + // AUIPC�? + 17'bxxxxxxx_xxx_0010111 : o_res <= pc_plus_imm ; // AUIPC + // 算术�? + 17'b0000000_000_0110011 : o_res <= i_num1u + i_num2u; // ADD + 17'bxxxxxxx_000_0010011 : o_res <= num1_plus_imm ; // ADDI + 17'b0100000_000_0110011 : o_res <= i_num1u - i_num2u; // SUB + // 逻辑�? + 17'b0000000_100_0110011 : o_res <= i_num1u ^ i_num2u; // XOR + 17'bxxxxxxx_100_0010011 : o_res <= i_num1u ^ i_immu ; // XORI + 17'b0000000_110_0110011 : o_res <= i_num1u | i_num2u; // OR + 17'bxxxxxxx_110_0010011 : o_res <= i_num1u | i_immu ; // ORI + 17'b0000000_111_0110011 : o_res <= i_num1u & i_num2u; // AND + 17'bxxxxxxx_111_0010011 : o_res <= i_num1u & i_immu ; // ANDI + // 位移�? + 17'b0000000_001_0110011 : o_res <= i_num1u << shamt_rs ; // SLL + 17'b0000000_001_0010011 : o_res <= i_num1u << shamt_imm; // SLLI + 17'b0000000_101_0110011 : o_res <= i_num1u >> shamt_rs ; // SRL + 17'b0000000_101_0010011 : o_res <= i_num1u >> shamt_imm; // SRL + 17'b0100000_101_0110011 : begin // SRA + o_res <= i_num1u >> shamt_rs; + for(int i=0;i< shamt_rs;i++) o_res[31-i] <= i_num1u[31]; + end + 17'b0100000_101_0010011 : begin // SRAI + o_res <= i_num1u >> shamt_imm; + for(int i=0;i=INSTR_CNT) ? 0 : instr_rom_cell[cell_rd_addr]; + else + bus.rd_data <= 0; + end + +endmodule + diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/naive_bus.sv b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/naive_bus.sv new file mode 100644 index 0000000..7e6ded4 --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/naive_bus.sv @@ -0,0 +1,26 @@ + +interface naive_bus(); + // read interface + logic rd_req, rd_gnt; + logic [3:0] rd_be; + logic [31:0] rd_addr, rd_data; + // write interface + logic wr_req, wr_gnt; + logic [3:0] wr_be; + logic [31:0] wr_addr, wr_data; + + modport master( + output rd_req, rd_be, rd_addr, + input rd_data, rd_gnt, + output wr_req, wr_be, wr_addr, wr_data, + input wr_gnt + ); + + modport slave( + input rd_req, rd_be, rd_addr, + output rd_data, rd_gnt, + input wr_req, wr_be, wr_addr, wr_data, + output wr_gnt + ); + +endinterface diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/ram.sv b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/ram.sv new file mode 100644 index 0000000..11dd81b --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/ram.sv @@ -0,0 +1,19 @@ +module ram( // 1024B + input logic clk, + input logic i_we, + input logic [ 9:0] i_waddr, i_raddr, + input logic [ 7:0] i_wdata, + output logic [ 7:0] o_rdata +); +initial o_rdata = 8'h0; + +logic [7:0] data_ram_cell [0:1023]; + +always @ (posedge clk) + o_rdata <= data_ram_cell[i_raddr]; + +always @ (posedge clk) + if(i_we) + data_ram_cell[i_waddr] <= i_wdata; + +endmodule diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/ram128B.sv b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/ram128B.sv new file mode 100644 index 0000000..83cc133 --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/ram128B.sv @@ -0,0 +1,19 @@ +module ram128B( // 128B + input logic clk, + input logic i_we, + input logic [ 6:0] i_addr, + input logic [ 7:0] i_wdata, + output logic [ 7:0] o_rdata +); +initial o_rdata = 8'h0; + +logic [7:0] data_ram_cell [0:127]; + +always @ (posedge clk) + o_rdata <= data_ram_cell[i_addr]; + +always @ (posedge clk) + if(i_we) + data_ram_cell[i_addr] <= i_wdata; + +endmodule \ No newline at end of file diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/soc_top.sv b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/soc_top.sv new file mode 100644 index 0000000..1cb2220 --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/soc_top.sv @@ -0,0 +1,138 @@ +module soc_top #( + parameter UART_RX_CLK_DIV = 108, // 50MHz/4/115200Hz=108 + parameter UART_TX_CLK_DIV = 434, // 50MHz/1/115200Hz=434 + parameter VGA_CLK_DIV = 1 +)( + // clock, typically 50MHz, UART_RX_CLK_DIV and UART_TX_CLK_DIV and VGA_CLK_DIV must be modify when clk is not 50MHz + input logic clk, + // debug uart and user uart shared signal + input logic isp_uart_rx, + output logic isp_uart_tx, + // SEG + output [7:0] SEL, + output [7:0] DIG, + // VGA signal + output logic vga_hsync, vga_vsync, + output logic vga_red, vga_green, vga_blue +); + +logic rst_n; +logic [31:0] boot_addr; +logic [31:0] rd_data ; +logic rd_gnt ; +logic wr_req ; +logic [31:0] wr_addr ; +logic [31:0] wr_data ; +logic wr_gnt ; + +naive_bus bus_masters[3](); +naive_bus bus_slaves[6](); + +assign rd_data = bus_slaves[5].rd_data ; +assign rd_gnt = bus_slaves[5].rd_gnt ; +assign wr_req = bus_slaves[5].wr_req ; +assign wr_addr = bus_slaves[5].wr_addr ; +assign wr_data = bus_slaves[5].wr_data ; +assign wr_gnt = bus_slaves[5].wr_gnt ; + +// shared debug uart and user uart module +isp_uart #( + .UART_RX_CLK_DIV ( UART_RX_CLK_DIV), + .UART_TX_CLK_DIV ( UART_TX_CLK_DIV) +) isp_uart_inst( + .clk ( clk ), + .i_uart_rx ( isp_uart_rx ), + .o_uart_tx ( isp_uart_tx ), + .o_rst_n ( rst_n ), + .o_boot_addr ( boot_addr ), + .bus ( bus_masters[0] ), + .user_uart_bus ( bus_slaves[4] ) +); + +// RV32I Core +core_top core_top_inst( + .clk ( clk ), + .rst_n ( rst_n ), + .i_boot_addr ( boot_addr ), + .instr_master ( bus_masters[2] ), + .data_master ( bus_masters[1] ) +); + +// 指令ROM +instr_rom instr_rom_inst( + .clk ( clk ), + .rst_n ( rst_n ), + .bus ( bus_slaves[0] ) +); + +// 指令RAM +ram_bus_wrapper instr_ram_inst( + .clk ( clk ), + .rst_n ( rst_n ), + .bus ( bus_slaves[1] ) +); + +// 数据RAM +ram_bus_wrapper data_ram_inst( + .clk ( clk ), + .rst_n ( rst_n ), + .bus ( bus_slaves[2] ) +); + + +// 显存 +video_ram #( + .VGA_CLK_DIV ( VGA_CLK_DIV ) +)video_ram_inst( + .clk ( clk ), + .rst_n ( rst_n ), + .bus ( bus_slaves[3] ), + .o_vsync ( vga_vsync ), + .o_hsync ( vga_hsync ), + .o_red ( vga_red ), + .o_green ( vga_green ), + .o_blue ( vga_blue ) +); + + +//SEG +pout_seg p0( + .clk (clk ), + .rst_n (rst_n ), + .SEL (SEL ), + .DIG (DIG ), + .rd_data (rd_data ), + .rd_gnt (rd_gnt ), + .wr_req (wr_req ), + .wr_addr (wr_addr ), + .wr_data (wr_data ), + .wr_gnt (wr_gnt ) +); + +// 3��?5从�?�线仲裁��? +// +// 主（越靠前优先级越高）： +// 0. UART Debugger? +// 1. Core Data Master +// 2. Core Instruction Master +// +// 从： +// 1. 指令ROM��? 地址空间 00000000~00000fff +// 2. 指令RAM��? 地址空间 00008000~00008fff +// 3. 数据RAM��? 地址空间 00010000~00010fff +// 4. 显存RAM��? 地址空间 00020000~00020fff +// 5. 用户UART�? 地址空间 00030000~00030003 +naive_bus_router #( + .N_MASTER ( 3 ), + .N_SLAVE ( 6 ), + .SLAVES_MASK ( {32'h0000_000f , 32'h0000_0003 , 32'h0000_0fff , 32'h0000_0fff , 32'h0000_0fff , 32'h0000_0fff } ), + .SLAVES_BASE ( {32'h0003_1000 , 32'h0003_0000 , 32'h0002_0000 , 32'h0001_0000 , 32'h0000_8000 , 32'h0000_0000 } ) +) soc_bus_router_inst ( + .clk ( clk ), + .rst_n ( rst_n ), + .masters ( bus_masters ), + .slaves ( bus_slaves ) +); + +endmodule + diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/uart_rx.sv b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/uart_rx.sv new file mode 100644 index 0000000..003e9e1 --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/uart_rx.sv @@ -0,0 +1,53 @@ +module uart_rx #( + parameter UART_RX_CLK_DIV = 108 // 50MHz/4/115200Hz=108 +)( + input logic clk, + input logic i_rx, + output logic o_ready, + output logic [7:0] o_data +); + +logic rx_bit, busy, last_busy=1'b0; +logic [ 5:0] shift = 6'h0, status = 6'h0; +logic [ 7:0] databuf = 8'h0; +logic [31:0] cnt = 0; + +initial o_ready = 1'b0; +initial o_data = 8'h0; + +assign busy = (status!=6'h0); +assign rx_bit = (shift[0]&shift[1]) | (shift[0]&i_rx) | (shift[1]&i_rx); + +always @ (posedge clk) + last_busy <= busy; + +always @ (posedge clk) + o_ready <= (~busy & last_busy); + +always @ (posedge clk) + cnt <= (cnt7'd0; +always @ (posedge clk) + busy_latch <= busy; + +assign tx_buffer = {2'b11, 8'h0A , // 0x0A = \n , a end of line + 2'b01, i_data[0], + 2'b01, i_data[1], + 2'b01, i_data[2], + 2'b01, i_data[3], + 2'b01, i_data[4], + 2'b01, i_data[5], + 2'b01, i_data[6], + 2'b01, i_data[7], + 2'b01, 8'b11111111 }; + +always @ (posedge clk) + cnt <= (cnt5'd0) begin + if(cnt==0) begin + if(tx_cnt==TX_CNT) begin + {tx_shift, o_uart_tx} <= ~{fifo_rd_data, 1'b1}; + fifo_rd_pointer <= fifo_rd_pointer + 10'h1; + end else begin + {tx_shift, o_uart_tx} <= {1'b0, tx_shift[7:1], ~tx_shift[0]}; + end + tx_cnt <= tx_cnt - 5'd1; + end + end else begin + o_uart_tx <= 1'b1; + tx_cnt <= fifo_empty ? 5'd0 : TX_CNT; + end + end + +ram ram_for_uart_tx_fifo_inst( + .clk ( clk ), + .i_we ( bus.wr_req & wr_addr_valid & bus.wr_be[0] & ~fifo_full ), + .i_waddr ( fifo_wr_pointer ), + .i_wdata ( bus.wr_data[7:0] ), + .i_raddr ( fifo_rd_pointer ), + .o_rdata ( fifo_rd_data ) +); + +endmodule diff --git a/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/vga_char_86x32.sv b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/vga_char_86x32.sv new file mode 100644 index 0000000..3233b56 --- /dev/null +++ b/hardware/Vivado/E-ELEMENTS/RISC-V.srcs/sources_1/imports/RTL/vga_char_86x32.sv @@ -0,0 +1,188 @@ +module vga_char_86x32 #( + parameter VGA_CLK_DIV = 1 +)( + // clock + input logic clk, rst_n, + // vga interfaces + output logic hsync, vsync, + output logic red, green, blue, + // user interface + output logic req, + output logic [11:0] addr, + input logic [ 7:0] ascii +); +localparam H_END = 10'd688, + H_BRSTART = H_END + 10'd4 , + H_BREND = H_BRSTART + 10'd30 , + H_SYNCSTART = H_BREND + 10'd25 , + H_SYNCEND = H_SYNCSTART + 10'd128, + H_BLSTART = H_SYNCEND + 10'd89 , + H_BLEND = H_BLSTART + 10'd30 , + H_PERIOD = H_BLEND + 10'd4 , + V_END = 10'd512, + V_BRSTART = V_END + 10'd4 , + V_BREND = V_BRSTART + 10'd30 , + V_SYNCSTART = V_BREND + 10'd38 , + V_SYNCEND = V_SYNCSTART + 10'd4 , + V_BLSTART = V_SYNCEND + 10'd66 , + V_BLEND = V_BLSTART + 10'd30 , + V_PERIOD = V_BLEND + 10'd4 ; + +logic [3:0] rlp=4'h0, clp=4'h0, hsp=4'h0, vsp=4'h0; +logic vlbr=1'b0, vgbl=1'b0, vlbl=1'b0, vgbr=1'b0, hlbr=1'b0, hgbl=1'b0, hlbl=1'b0, hgbr=1'b0; +logic vir=1'b0, hir=1'b0, vbr=1'b0, hbr=1'b0, vbl=1'b0, hbl=1'b0, hb=1'b0, vb=1'b0, border=1'b0; +logic [9:0] cnt = 0, hcnt = 0, vcnt = 0; +logic req1 = 1'b0, req2 = 1'b0; +logic [7:0] ascii_bufferout, ascii_latch=8'h0, ascii_to_rom; +logic [7:0] rom_data; +logic [6:0] x_h, x_h1=7'h0, x_h2=7'h0; +logic [5:0] y_h; + +logic [2:0] x_l, x_l1 = 3'h0, x_l2 = 3'h0, x_l3 = 3'h0, x_l4 = 3'h0; +logic [3:0] y_l, y_l1 = 4'h0, y_l2 = 4'h0, y_l3 = 4'h0; + +assign {x_h, x_l} = hcnt; +assign {y_h, y_l} = vcnt; + +initial begin hsync=1'b0; vsync=1'b0; {red,green,blue}=3'h0; req=1'b0; addr = 12'h0; end + +always @ (posedge clk) + if(~rst_n) begin + vlbr<= 1'b0; + vgbl<= 1'b0; + vlbl<= 1'b0; + vgbr<= 1'b0; + hlbr<= 1'b0; + hgbl<= 1'b0; + hlbl<= 1'b0; + hgbr<= 1'b0; + vir <= 1'b0; + hir <= 1'b0; + vbr <= 1'b0; + hbr <= 1'b0; + vbl <= 1'b0; + hbl <= 1'b0; + hb <= 1'b0; + vb <= 1'b0; + border <= 1'b0; + end else begin + vlbr<= vcnt < V_BREND ; + vgbl<= vcnt >= V_BLSTART; + vlbl<= vcnt < V_BLEND ; + vgbr<= vcnt >= V_BRSTART; + hlbr<= hcnt < H_BREND ; + hgbl<= hcnt >= H_BLSTART; + hlbl<= hcnt < H_BLEND; + hgbr<= hcnt >= H_BRSTART; + vir <= vlbr | vgbl; + hir <= hlbr | hgbl; + vbr <= vgbr & vlbr; + hbr <= hgbr & hlbr; + vbl <= vgbl & vlbl; + hbl <= hgbl & hlbl; + hb <= (hbr | hbl) & vir; + vb <= (vbr | vbl) & hir; + border <= hb | vb; + end + +always @ (posedge clk or negedge rst_n) + if(~rst_n) begin + cnt <= 10'h0; + hcnt <= 10'h0; + vcnt <= 10'h0; + end else begin + cnt <= (cnt<(VGA_CLK_DIV-1)) ? cnt + 10'h1 : 10'h0; + if(cnt==10'h0) begin + if(hcnt < H_PERIOD) begin + hcnt <= hcnt + 10'h1; + end else begin + hcnt <= 10'h0; + vcnt <= (vcnt=H_SYNCSTART && hcnt=V_SYNCSTART && vcnt + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + + + +