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lines changedSubmodule llvm-project updated 90 files
- .github/workflows/release-binaries.yml+13-2
- .github/workflows/release-sources.yml+1-1
- clang/docs/ReleaseNotes.rst+3
- clang/lib/Basic/Targets/X86.cpp+4
- clang/lib/CodeGen/CGCall.cpp+61-85
- clang/lib/CodeGen/CGExprAgg.cpp+14-9
- clang/lib/CodeGen/CGStmt.cpp+1-1
- clang/lib/CodeGen/CodeGenFunction.h+4-3
- clang/lib/Format/UnwrappedLineParser.cpp+4-2
- clang/lib/Sema/SemaExpr.cpp+17-4
- clang/lib/Sema/SemaExprCXX.cpp+2-1
- clang/lib/Sema/SemaLambda.cpp-1
- clang/lib/Sema/SemaLookup.cpp+1-1
- clang/lib/StaticAnalyzer/Core/ExprEngine.cpp+1-4
- clang/test/Analysis/embed.c+12
- clang/test/CodeGen/arm-mve-intrinsics/vld24.c+27-16
- clang/test/CodeGen/arm-vfp16-arguments2.cpp+5-5
- clang/test/CodeGen/target-builtin-noerror.c+1
- clang/test/CodeGenCUDA/amdgpu-kernel-arg-pointer-type.cu+4-7
- clang/test/CodeGenCUDA/builtins-amdgcn.cu+58-67
- clang/test/CodeGenCUDA/builtins-spirv-amdgcn.cu+57-66
- clang/test/CodeGenCXX/address-space-cast-coerce.cpp+3-3
- clang/test/CodeGenCXX/cxx2a-consteval.cpp+23-1
- clang/test/CodeGenCXX/trivial_abi.cpp+20
- clang/test/CodeGenHIP/dpp-const-fold.hip+4-4
- clang/test/CodeGenHIP/spirv-amdgcn-dpp-const-fold.hip+4-4
- clang/test/CodeGenOpenCL/addr-space-struct-arg.cl+9-2
- clang/test/CodeGenOpenCL/amdgpu-abi-struct-arg-byref.cl+27-15
- clang/test/Driver/x86-march.c+4
- clang/test/Frontend/x86-target-cpu.c+1
- clang/test/Misc/target-invalid-cpu-note.c+4-4
- clang/test/Preprocessor/predefined-arch-macros.c+142
- clang/test/SemaCXX/cxx23-assume.cpp+9
- clang/test/SemaCXX/cxx2c-placeholder-vars.cpp+4-2
- clang/test/SemaCXX/source_location.cpp+60
- clang/test/SemaCXX/type-traits.cpp+18
- clang/unittests/Format/TokenAnnotatorTest.cpp+15
- cmake/Modules/LLVMVersion.cmake+1-1
- compiler-rt/lib/builtins/cpu_model/x86.c+20
- compiler-rt/lib/builtins/divtc3.c+1-1
- compiler-rt/lib/builtins/multc3.c+1-1
- libcxx/include/chrono+1-1
- lld/ELF/Arch/Hexagon.cpp+3-5
- lld/test/ELF/hexagon-eflag.s+5
- llvm/docs/ReleaseNotes.rst+4
- llvm/include/llvm/TargetParser/X86TargetParser.def+3
- llvm/include/llvm/TargetParser/X86TargetParser.h+1
- llvm/lib/CodeGen/ModuloSchedule.cpp+3
- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp+4
- llvm/lib/IR/BasicBlock.cpp+10-2
- llvm/lib/Target/AArch64/AArch64FrameLowering.cpp-33
- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp-4
- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp+18-12
- llvm/lib/Target/PowerPC/PPCISelLowering.cpp+5-4
- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp+1-1
- llvm/lib/Target/X86/X86.td+15
- llvm/lib/Target/X86/X86PfmCounters.td+1
- llvm/lib/TargetParser/Host.cpp+19
- llvm/lib/TargetParser/X86TargetParser.cpp+5
- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp+7-1
- llvm/test/CodeGen/AArch64/sme-vg-to-stack.ll+66-38
- llvm/test/CodeGen/AArch64/sme2-intrinsics-ld1.ll+944-544
- llvm/test/CodeGen/AArch64/sme2-intrinsics-ldnt1.ll+944-544
- llvm/test/CodeGen/AArch64/spillfill-sve.mir+36-1
- llvm/test/CodeGen/AArch64/sve-callee-save-restore-pairs.ll+82-58
- llvm/test/CodeGen/AMDGPU/mul_int24.ll+98
- llvm/test/CodeGen/Hexagon/swp-ws-live-intervals.mir+217
- llvm/test/CodeGen/PowerPC/f128-bitcast.ll+22
- llvm/test/CodeGen/RISCV/machineoutliner-pcrel-lo.mir+98-6
- llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll+18
- llvm/test/CodeGen/X86/bypass-slow-division-64.ll+1
- llvm/test/CodeGen/X86/cmp16.ll+1
- llvm/test/CodeGen/X86/cpus-amd.ll+1
- llvm/test/CodeGen/X86/rdpru.ll+1
- llvm/test/CodeGen/X86/shuffle-as-shifts.ll+1
- llvm/test/CodeGen/X86/slow-unaligned-mem.ll+1
- llvm/test/CodeGen/X86/sqrt-fastmath-tune.ll+1
- llvm/test/CodeGen/X86/tuning-shuffle-permilpd-avx512.ll+1
- llvm/test/CodeGen/X86/tuning-shuffle-permilps-avx512.ll+1
- llvm/test/CodeGen/X86/tuning-shuffle-unpckpd-avx512.ll+1
- llvm/test/CodeGen/X86/tuning-shuffle-unpckps-avx512.ll+1
- llvm/test/CodeGen/X86/vector-shuffle-fast-per-lane.ll+1
- llvm/test/CodeGen/X86/vpdpwssd.ll+1
- llvm/test/CodeGen/X86/x86-64-double-shifts-var.ll+1
- llvm/test/MC/X86/x86_long_nop.s+2
- llvm/test/Transforms/LoopUnroll/X86/call-remark.ll+1
- llvm/test/Transforms/SLPVectorizer/X86/minbw-user-non-sizable.ll+31
- llvm/test/Transforms/SLPVectorizer/X86/operand-is-reduced-val.ll+49
- llvm/test/Transforms/SLPVectorizer/X86/pr63668.ll+1
- llvm/unittests/IR/BasicBlockDbgInfoTest.cpp+52
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