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Description
Hi WeiChung,
Thanks for you SystemVerilog plugins, it helps me a lot in implenting verification environment.
I am writing to ask for one enhancement of this plugins for uvm_info sentences.
If we start one "if" block, the third lines will deindent automically if there is ':' in the seconde line. The example is as below:

I am very happy witht the implement now that the third line will deindent. However, if the sencond line is a uvm Macro, which has no ':', the third line will not deindent. Examples:

I wondering is it possible to add the support for such scenarios? The scenarios could be as following also:


I understand that process all the Macros without ':' could be very difficult as it may need verilog syntax compiler help. However, if we limit the macros of the second line to uvm_info/uvm_error/uvm_warning/uvm_fatal, is it possible to support the de-indent automically at third line?
Thanks & Regards
Yuhao