add legacy code

Author: WilliamZhang20

docs/info.md

@@ -9,12 +9,12 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Explain how your project works
+The project is an AI chip inspired by Google's TPU. It multiply 8-bit floating-point valued matrices. It does so by tiling in 2x2 to fit on the chip's tiny area, so expect performance degradation compared to regular chips. However, the chip's I/O bandwidth will be fully utilized and saturated.
 
 ## How to test
 
-Explain how to use your project
+Use cocotb and [pyuvm](https://github.com/pyuvm/pyuvm) to lean towards [IEEE-1800.2](https://blogs.sw.siemens.com/verificationhorizons/2015/07/30/uvm-the-next-ieee-standard-1800-2/).
 
 ## External hardware
 
-List external hardware used in your project (e.g. PMOD, LED display, etc), if any
+Connect the PCB board with the Tiny Tapeout chips (a.k.a. a Raspberry Pi) to a personal computer via USB.

info.yaml

@@ -1,56 +1,62 @@
 # Tiny Tapeout project information
 project:
-  title:        ""      # Project title
-  author:       ""      # Your name
-  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  ""      # One line description of what your project does
+  title:        "Tensor Processing Unit v2"      # Project title
+  author:       "William Zhang"      # Your name
+  discord:      "walrus_23"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "multiplies fp8 matrices"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
-  clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
+  clock_hz:     50000000       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
+  tiles: "1x2"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
   # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
+  top_module:  "tt_um_tpu"
 
   # List your project's source files here.
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
-    - "project.v"
+    - "tpu.v"
+    - "systolic_array_2x2.v"
+    - "PE.v"
+    - "memory.v"
+    - "control_unit.v"
+    - "mmu_feeder.v"
+    - "delay_cell.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 # This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).
 pinout:
   # Inputs
-  ui[0]: ""
-  ui[1]: ""
-  ui[2]: ""
-  ui[3]: ""
-  ui[4]: ""
-  ui[5]: ""
-  ui[6]: ""
-  ui[7]: ""
+  ui[0]: "IN0"
+  ui[1]: "IN1"
+  ui[2]: "IN2"
+  ui[3]: "IN3"
+  ui[4]: "IN4"
+  ui[5]: "IN5"
+  ui[6]: "IN6"
+  ui[7]: "IN7"
 
   # Outputs
-  uo[0]: ""
-  uo[1]: ""
-  uo[2]: ""
-  uo[3]: ""
-  uo[4]: ""
-  uo[5]: ""
-  uo[6]: ""
-  uo[7]: ""
+  uo[0]: "OUT0"
+  uo[1]: "OUT1"
+  uo[2]: "OUT2"
+  uo[3]: "OUT3"
+  uo[4]: "OUT4"
+  uo[5]: "OUT5"
+  uo[6]: "OUT6"
+  uo[7]: "OUT7"
 
   # Bidirectional pins
-  uio[0]: ""
-  uio[1]: ""
-  uio[2]: ""
-  uio[3]: ""
-  uio[4]: ""
-  uio[5]: ""
-  uio[6]: ""
-  uio[7]: ""
+  uio[0]: "LOAD_EN (input)"
+  uio[1]: "TRANSPOSE (input)"
+  uio[2]: "ACTIVATION (input)"
+  uio[3]: "Unused"
+  uio[4]: "Unused"
+  uio[5]: "Unused"
+  uio[6]: "Unused"
+  uio[7]: "DONE (output)"
 
 # Do not change!
-yaml_version: 6
+yaml_version: 6

src/PE.v

@@ -0,0 +1,30 @@
+module PE #(
+    parameter WIDTH = 8
+)(
+    input wire clk,
+    input wire rst,
+    input wire clear,
+    input wire signed [WIDTH-1:0] a_in,
+    input wire signed [WIDTH-1:0] b_in,
+
+    output reg signed [WIDTH-1:0] a_out,
+    output reg signed [WIDTH-1:0] b_out,
+
+    output reg signed [WIDTH*2-1:0] c_out
+);
+
+    always @(posedge clk) begin
+        a_out <= a_in;
+        b_out <= b_in;
+        if (rst) begin
+            c_out <= 0;
+            a_out <= 0;
+            b_out <= 0;
+        end else if (clear) begin
+            c_out <= a_in * b_in;
+        end else begin
+            c_out <= c_out + (a_in * b_in);
+        end
+    end
+
+endmodule

src/config.json

@@ -13,15 +13,15 @@
 
   "//": "PL_TARGET_DENSITY_PCT - You can increase this if Global Placement fails with error GPL-0302.",
   "//": "Users have reported that values up to 80 worked well for them.",
-  "PL_TARGET_DENSITY_PCT": 60,
+  "PL_TARGET_DENSITY_PCT": 80,
 
   "//": "CLOCK_PERIOD - Increase this in case you are getting setup time violations.",
   "//": "The value is in nanoseconds, so 20ns == 50MHz.",
   "CLOCK_PERIOD": 20,
 
   "//": "Hold slack margin - Increase them in case you are getting hold violations.",
-  "PL_RESIZER_HOLD_SLACK_MARGIN": 0.1,
-  "GRT_RESIZER_HOLD_SLACK_MARGIN": 0.05,
+  "PL_RESIZER_HOLD_SLACK_MARGIN": 0.5,
+  "GRT_RESIZER_HOLD_SLACK_MARGIN": 0.4,
 
   "//": "RUN_LINTER, LINTER_INCLUDE_PDK_MODELS - Disabling the linter is not recommended!",
   "RUN_LINTER": 1,
@@ -31,7 +31,7 @@
   "//": "https://tinytapeout.com/faq/#how-can-i-map-an-additional-external-clock-to-one-of-the-gpios",
   "CLOCK_PORT": "clk",
 
-  "//": "Configuration docs: https://librelane.readthedocs.io/en/latest/reference/configuration.html",
+  "//": "Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html",
 
   "//": "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!",
   "//": "!!! DO NOT CHANGE ANYTHING BELOW THIS POINT !!!",
@@ -63,12 +63,13 @@
   "//": "Clock",
   "RUN_CTS": 1,
 
-  "//": "Don't generate power rings",
+  "//": "Don't use power rings or met5 layer",
   "FP_PDN_MULTILAYER": 0,
+  "RT_MAX_LAYER": "met4",
 
   "//": "MAGIC_DEF_LABELS may cause issues with LVS",
   "MAGIC_DEF_LABELS": 0,
 
   "//": "Only export pin area in LEF (without any connected nets)",
   "MAGIC_WRITE_LEF_PINONLY": 1
-}
+}

src/control_unit.v

@@ -0,0 +1,129 @@
+`default_nettype none
+
+module control_unit (
+    input wire clk,
+    input wire rst,
+    input wire load_en,
+
+    // Memory interface  
+    output reg [2:0] mem_addr,
+
+    // MMU feeding control
+    output reg mmu_en,
+    output reg [2:0] mmu_cycle,
+
+    // For debugging
+    output wire [1:0] state_out
+);
+
+    // STATES
+    localparam [1:0] S_IDLE                  = 2'b00;
+    localparam [1:0] S_LOAD_MATS             = 2'b01;
+    localparam [1:0] S_MMU_FEED_COMPUTE_WB   = 2'b10;
+
+    reg [1:0] state, next_state;
+
+    assign state_out = state;
+
+    // Next state logic
+    always @(*) begin
+        next_state = state;
+
+        case (state)
+            S_IDLE: begin
+                if (load_en) begin
+                    next_state = S_LOAD_MATS;
+                end
+            end
+            
+            S_LOAD_MATS: begin
+                // All 8 elements loaded (4 for each matrix)
+                if (mem_addr == 3'b111) begin 
+                    next_state = S_MMU_FEED_COMPUTE_WB;
+                end
+            end
+            
+            S_MMU_FEED_COMPUTE_WB:
+                next_state = S_MMU_FEED_COMPUTE_WB;
+               /* MMU CYCLE PATTERN
+                * Cycle 0: Start feeding data (a00×b00 starts)
+                * Cycle 1: First partial products computed, more data fed
+                * Cycle 2: c00 ready (a00×b00 + a01×b10), is output, while take in next a00
+                * Cycle 3: c01 and c10 ready simultaneously, read next a01:
+                *          c01 = a00×b01 + a01×b11
+                *          c10 = a10×b00 + a11×b10
+                * Cycle 4: c11 ready (a10×b01 + a11×b11), read next a10
+                * Cycle 5: All outputs remain valid, read next a11
+                * Cycle 6: Keep outputting, read next b00
+                * Cycle 7: Keep outputting, read next b01
+                * Back to cycle 0: Start feeding data (a00×b00 starts), keep outputting, read next b10
+                * Cycle 1: First partial products computed, keep outputting, read next b01
+                * Cycle 2: c00 ready, begin output, take in next a00, pattern continues...
+                */
+
+			default: begin
+				next_state = S_IDLE;
+			end
+        endcase
+    end
+
+    // State Machine
+    always @(posedge clk) begin
+        if (rst) begin
+            state <= S_IDLE;
+            mmu_cycle <= 0;
+            mmu_en <= 0;
+            mem_addr <= 0;
+        end else begin
+            state <= next_state;
+            mem_addr <= 0;
+            case (state)
+                S_IDLE: begin
+                    mmu_cycle <= 0;
+                    mmu_en <= 0;
+                    if (load_en) begin
+                        mem_addr <= mem_addr + 1;
+                    end
+                end
+
+                S_LOAD_MATS: begin
+                    if (load_en) begin
+                        mem_addr <= mem_addr + 1;
+                    end
+
+                    if (mem_addr == 3'b101) begin
+                        mmu_en <= 1;
+                    end else if (mem_addr >= 3'b110) begin
+                        mmu_en <= 1;
+                        mmu_cycle <= mmu_cycle + 1;
+                        if (mem_addr == 3'b111) begin 
+                            mem_addr <= 0;
+                        end
+                    end
+                end
+
+                S_MMU_FEED_COMPUTE_WB: begin
+                    // Now: the TPU will be forever stuck in this cycle...
+                    // Cycles through counter of 8...
+                    // In each cycle of 8 counts, it will: output 4 16-bit output elements the result of the previous matmul,
+                    // and take in 8 new 8-bit elements
+                    if (load_en) begin
+                        mem_addr <= mem_addr + 1;
+                    end
+					mmu_cycle <= mmu_cycle + 1; // allow mmu_cycle to continue incrementing, permitting a pipeline flush
+                    if (mmu_cycle == 3'b111) begin
+                        mmu_cycle <= 0;
+                    end else if (mmu_cycle == 1) begin
+                        mem_addr <= 0;
+                    end
+                end
+				
+				default: begin
+                    mmu_cycle <= 0;
+                    mmu_en <= 0;
+				end
+            endcase
+        end
+    end
+
+endmodule

src/delay_cell.v

@@ -0,0 +1,15 @@
+module buffer (
+    output wire X   ,
+    input  wire A   ,
+    input  wire VPWR,
+    input  wire VGND,
+    input  wire VPB ,
+    input  wire VNB
+);
+
+    assign X = A;
+
+    wire _unused;
+    assign _unused = &{ 1'b0, VPWR, VGND, VPB, VNB };
+
+endmodule

src/memory.v

@@ -0,0 +1,36 @@
+`default_nettype none
+
+module memory (
+    input wire clk,
+    input wire rst,
+    input wire load_en,
+    input wire [2:0] addr, // MSB selects matrix (0: weights, 1: inputs), [1:0] selects element
+    input wire [7:0] in_data, // Fixed from reg to wire to match tt_um_tpu.v
+    output wire [7:0] weight0, weight1, weight2, weight3, // 2x2 matrix A elements, 1 byte each
+    output wire [7:0] input0, input1, input2, input3 // 2x2 matrix B elements, 1 byte each
+);
+
+    reg [7:0] sram [0:7]; // 8 locations: 0-3 for weights, 4-7 for inputs
+    integer i;
+
+    always @(posedge clk) begin
+        if (rst) begin
+            for (i = 0; i < 8; i = i + 1) begin
+                sram[i] <= 8'b0;
+            end
+        end else if (load_en) begin
+            sram[addr] <= in_data;
+        end
+    end
+
+    // asynchronous read
+    assign weight0 = sram[0];
+    assign weight1 = sram[1];
+    assign weight2 = sram[2];
+    assign weight3 = sram[3];
+    assign input0 = sram[4];
+    assign input1 = sram[5];
+    assign input2 = sram[6];
+    assign input3 = sram[7];
+
+endmodule